With the development of technology,the performance of portable devices such as cell phones,laptops and Bluetooth headsets has increased time and again,which requires power management chips to face more complex power supply requirements.DC-DC converters are required to be able to output not only low voltage and high current,but also low voltage ripple in different applications.In contrast to single-phase BUCK converters,multi-phase BUCK converters must solve two problems: current balancing and accurate phase shifting.In this paper,we use the idea of current sampling,where the sampled current is compared with the peak inductor current error and then superimposed into the loop thereby achieving current balancing.Conventional pulse width modulation(PWM)controllers with constant switching frequency are suitable for multi-phase BUCK converters,so the controller structure is chosen for PWM voltage mode control and the compensation method is chosen for type III compensation.In order to meet different power requirements,this paper conducts a study on DC-DC converters with wide input range,low voltage output and low ripple characteristics,and the main work is as follows:I.The theoretical study and simulation of the topology of the multi-phase BUCK converter based on the analysis of the basic principles of single-phase BUCK.II.Design the corresponding key circuits in the multiphase BUCK circuit for the general layout.Among them,the key technologies of this converter chip are mainly studied,including current equalization,correct phase shift control,error amplifier circuit for larger DC gain,and stable loop compensation.III.The layout is drawn in sub-modules,then the corresponding PAD and ESD protection is added to the overall layout,and finally the overall post-imitation is performed.This paper is based on the Hua Hong 0.35 μm BCD process.Using Verilog-A modelling analysis,an input feed-forward synchronous buck PWM controller has been designed to control a dual independent voltage converter.The internal oscillator has a frequency range of 150 k Hz to 1.5 MHz and is capable of synchronising with an external clock signal for phase synchronisation applications.The phase-locked circuitry can output a programmable phase-shifted clock signal,allowing the system to be extended to 3,4,6 and 12 phases with the required interleaved phase-shifting capability.Efficient low voltage and high current outputs can easily be achieved through the multiphase cascade technique with easy operation.This technique is characterised by the ability to counteract output noise between multiple phases due to phase differences,while enabling accurate balancing of the total output current of each phase.The final VIN input range can be from 3V to 22 V,with a measured output voltage ripple of3.02 m V and a maximum load current of 25 A at a set input of 12 V and output of 1.2V. |