Research And Design Of Six-Phase Interleaved Parallel Buck DC-DC Converter

Since the 21st century,with the development of integrated circuits and the large-scale application of various system-on-chips(SOCs),the development of chip systems has gradually moved towards high speed,high integration,and miniaturization.Among them,the application of the processor microprocessor requires a high-precision power supply and a large output power.At the same time,in order to achieve the integration of the CPU and the power supply,therefore,the corresponding DC-DC converter is proposed to meet the requirements of low ripple,large output current and high integration.The scope of application of traditional DC-DC converters is gradually narrowing,and it is no longer applicable to new processors.In order to solve the above problems,this paper proposes a six-phase parallel interleaved fully integrated Buck circuit design.After comparing the different interleaved parallel methods,a current hysteresis control mode is adopted,and a new master-slave current sharing implementation method is proposed.The DCR current detection circuit is used to extract the change information of the inductor current of each phase,which is fed back to the external hysteresis comparison of each phase.The inverter locks the inductor current of each phase within a certain hysteresis width,selects one of the phases as the main phase loop,and uses the delay phase-locked loop to generate a pulse signal that differs from the main phase drive signal phase by 60 ° and superimposes it to the hysteresis.The lower limit of the loop,by dynamically adjusting the width of the hysteresis loop,makes the switching signals of each phase interleaved and divides the frequency to achieve a better current sharing effect while increasing the dynamic response speed.It is verified by simulation that this method can effectively achieve current sharing of each phase,to avoid excessive local current caused by uneven current distribution and damage to the device.Compared with the ordinary DC-DC converter,the six-phase parallel interleaving method can effectively increase the output current,reduce the ripple,and reduce the output capacitor inductance area.This article uses 0.18 um BCD process designed by TSMC.When the input voltage is 5V,the output range is 1.5V-2.2V,and the maximum output current is 5A.Compared with the traditional single-phase buck current,the six-phase parallel staggered structure can effectively reduce the output voltage ripple and the area of the filter capacitor,and the energy storage inductance value is dispersed due to the dispersed output current Reduce,the current difference of each phase is controlled within 16.6m A,and the output current ripple is within 71 mA.