Research On Key Technologies Of Identifier-to-Locator Mapping In Universal Identifier Networks

In the traditional Internet, the overloading of Internet Protocol (IP) addresses with the semantics of both "who"(endpoint identifiers) and "where"(locators for routing system) is considered to have deep implications for the routing scalability, which also causes the problems of mobility and security. Universal Identifier Networks (UIN) split IP addresses into Accessing Identifiers (AIDs) and Routing Identifiers (RIDs). In the new network architecture based on Identifier/Locator separation, the mapping between identifiers and locators becomes an important research topic.In UIN, mapping systems store and manage the mappings between AIDs and RIDs, and resolve the Map-Requests sent by Access Switching Routers (ASRs). Map-ping cache is used in ASRs to temporarily store the mappings of remote hosts, to reduce the mapping lookup latency. Mapping systems and mapping cache are indispensable to the communication in UIN. This dissertation researches on mapping systems, mapping cache based on Time-to-Live (TTL), mapping cache replacement policy and mapping cache consistency, to complete the mapping architecture and provide theoretical basis and technical support for the deployment of UIN. The main research innovations are outlined as follows:1. A Hierarchical Mapping System (HMS) is proposed in UIN, to support scalabil-ity and mobility better. The bottom level regards AIDs as flat identifiers and uses one-hop DHT to store the AID-to-RID mappings in an Autonomous System (AS). The upper level can highly aggregate the AIDs in an AS and propagates AID-prefix-to-AS mappings using a protocol like BGP. One-hop Distributed Hash Table (DHT) can reduce the mapping lookup latency and the highly aggregated AIDs can reduce the number of mapping items in the upper level, thus improving the scalability of HMS. Furthermore, HMS introduces the mobility management scheme to support host mobility. The trace driven simulation results and per-formance comparisons show that HMS has low load and resolution cost.2. When an ASR obtains a mapping from mapping systems, it stores the mapping into the mapping cache.In general, the mapping cache is based on TTL. There are two options to update the TTL of a mapping, designated as No-Reset (NR) and With-Reset (WR) modes. This dissertation compares the performance of the two modes in terms of cache hit rate, cache misses, mapping items and communication interruption probability, by building analytical models and doing trace driven simulation. The results show that when the cache timeout is the same, the WR mode can achieve higher cache hit rate and smaller communication interruption probability. Although the NR mode can set larger cache timeout to gain similar performance to the WR mode, it costs more resource. The analysis results provide rational for the mapping cache to use the WR mode.3. The mapping cache based on TTL does not consider the effect of cache size. To address the issue when the cache size is limited, this dissertation researches on the mapping cache replacement policies. Based on the temporal locality and the mapping request frequency distribution present in the mapping referencing behavior, three metrics are proposed to measure the performance of different replacement policies, including hit rate, communication interruption probability and cache eviction. The comparisons among different cache replacement policies show that, when the cache size is relatively large, the Least Recently Used (LRU) policy can achieve almost optimal cache hit rate and cause fewest communica-tion interruptions and cache evictions, which is suitable for the mapping cache replacement policy, both for flat and aggregatable AIDs.4. To address the problem of cache consistency caused by a mapping change, a mechanism to maintain strong cache consistency is proposed. TTL mechanism is a weak cache consistency scheme, and the evaluation on the performance of TTL indicates that maintaining strong mapping cache consistency has become an indispensable mechanism. To address this issue, the lease algorithm is proposed. This dissertation evaluates the performance of lease algorithm through analyt-ical modeling and trace driven simulation. The lease algorithm is compared to polling-every-time and invalidation by trace-driven simulation, in terms of the state space and control messages. The results show that the lease algorithm with an appropriate lease duration can balance the state space overhead and the control message overhead, while providing strong mapping cache consistency.