Research On Key Technologies Of Reuse Based Digital Integrated Circuits Design

The reuse methodology at system and gate level has become an important trend for the system-on-chip (SoC), and extraction of functional regularity automatically in digital ICs (Integrated Circuits) is playing a kernel role in regular design and IC analysis. This thesis focuses on the algorithm of the functional regularity automated extraction problem, and presents five main contributions as follows:1. In order to meet the needs of diversity and flexibility of IP (Intellectual Property) in SoC design, a customizable and reusable architecture for interface circuits is proposed, and based on this architecture, the CF (Compact Flash) card and MMC (Multi Media Card) host controller are realized. According to the common characteristics of interface control circuits, the interface controller circuits can be divided into three parts:the interface control section, the data path part and the transmission control part. Based on configurable and parametric design method, the IP core user can choose the function mode、FIFO (First In First Out) depth and width bus width and any other configuration freely. FPGA validation results show that the function of the interface host controllers can achieve the design goals.2. A new model named two-isomorphic is proposed to describe the circuit, and based on this model, a novel algorithm which can be used to extract the regularity in digital integrated circuits is achieved. By extracting and analyzing the properties of all two connected standard cells in the circuits, a series of templates including two standard cells will be obtained. The template with a high frequency will be extended so that it becomes longer than two, and then the instances of all longer templates will be explored using the proposed algorithm. To reduce the complexity and accelerate the algorithm, the matched vertexes will be deleted gradually from the search space. Experiments show that this method can reduce the complexity of the regular extraction, and extract the most frequent structural first.3. According to the problem of high complexity in extraction of functional regularity in digital ICs, a regularity pre-extraction algorithm named SFSE for small scale frequent subcircuits is proposed, which is capable of categorizing the root nodes gradually. By extending the frequent edges directly, the small frequent subcircuits can be extracted fast; and utilizing structure dependencies between small frequent subcircuits and big ones at gate level, the combination explosion problem of root nodes has been solved in the process of generating candidate subcircuits. Experimental results show that the proposed algorithm can reduce the number of root nodes effectively, extract the high frequency candidate subcircuits with high priority and reduce runtime of regularity extraction observably. It is anticipated that the data mining method may play an important complementary role to the extraction of regularity in digital ICs.4. By using the method of data mining in the extraction of functional regularity in digital ICs, two novel templates called CHAIN and FAN generation algorithms are proposed. To save the memory, a more efficient compressed storage strategy and deleting the buffer structure method are used when dealing with very large scale ICs. By establishing sequence-dependent edge-weight model, the complex subcircuit isomorphism problem can be solved by comparing the edge weight sequences of the subcircuits. To reduce the complexity and accelerate the algorithm, the pruning strategy is introduced into the expending of the templates to delete non-frequent subcircuits gradually. By merging the template generation process and the subcircuit isomorphism searching process, the regularity extraction flow is simplified. Meanwhile, the problem of high complexity during the extraction of functional regularity in very large scale ICs has been solved effectively. Experimental results show that both the CHAIN and FAN algorithms are more effective and can obtain better circuit covering results faster than the SPOG and TREE methods, furthermore, both of the two algorithms can be used as the pre-extraction algorithm to improve the performance of the traditional algorithms.5. Based on the extraction methods of frequent mode above, a gate level integrated circuit automatic analysis process is proposed, which can be used to enhance the work efficiency of traditional analysis. A circuit structure automatically display method based on EDIF file is proposed. With the help of two standard array methods of the cells, a series of extraction and identification methods for basic and special function structure are proposed, meanwhile, the structure models of counter and FSM are described. By successfully applying these methods to a32-bit ASIP and data-path circuits in Strong ARM, the validity of these methods are proved. These methods have been implemented successfully in industry projects, and replaced the traditional manual analysis at gate level. Furthermore, the complexity of the reverse analysis for VLSI is reduced, and the work efficiency can also be enhanced distinctly.