Research And Design Of Railway Balise System And Its Low Power, High Reliablity ASICs

In recent years, the railway and urban rail transit have made rapid development. However, the balise system, as the basic communication system in railway and urban rail transit, has been heavily dependent on imports for long periods. It is important to develop the domestic-made highly reiable balise system. At present, the balise technology is in its beginning stage. We analyze the imported balise to understand its functionality requirements, operating principle and system solution. The logic control module as the core unit of the balise is realised by an ASIC (Application Specific Integrated Circuit) for its low power, reliability and the technical privacy protection, which is a chanllenge for the domestic-made balise by reverse engineering.On the other hand, the reader/writer as a corollary equipment of the balise is often supplied to railway by the same company to ensure data security and maintainability. Because of the prohibitive costs of foreign products, it is difficult to design the homemade reader/writer based on a mature producet, which makes the self-developed reader/writer become an urgent problem.The main function of the reader/writer is to receive and demodulate FSK (Frequency Shift Keying) signals sent by the balise, and used to detect whether the balise is in a normal state. A new FSK demodulation algorithm with high BER performance is required to ensure the reader/writer that can works correctly and efficiently in complex conditions, such as large FSK noises.The balise is a necessary safety equipment for communication between the train and the ground, where the reliability of the logic control chip directly impacts the reliability of the balise. We introduce the mature TMR (Triple Modular Redundancy) technology into the balise ASIC to improve the reliability of the system. Obtaining energy through electromagnetic coupling sets strict restriction on power consumption of the balise. How to design a low power TMR ASIC become the key of the homemade balise.Based on the above requirements, this paper sets to study. The main contributions of this paper are the following:1. In order to obtain high reliability reader/wirter, this paper proposed a low BER all-digital coherent-like BFSK demodulation. The test results show that the BER and power consumption meet the requirement of the reader/writer and BER performance is better than that of the existing non-coherent demodulation algorithms. Meanwhile the FOM (Figure of Merit) of the proposed FSK demodulator is competitive with the state-of-the-art work.The research result of FSK demodulation has been published on SCI journal Microelectronics Journal Vol.45, No.6(2014.6). Besides, we finished the design and test of the reader/writer system and its ASIC chip based on the proposed FSK demodulation, the relate research has been published on SCI journal Journal of Circuits, Systems and Computers,Vol.22, No.9(2013.9).2. In order to solute the problem of the failure caused by the top voter in TMR chip, this paper proposed a substitutable DMV (Dual Modular Voter). It is proven that the proposed DMV is the only full fault tolerant voter by injecting an SET (Single Event Transient) into any internal node and it will not fail when suffer SET interference. However, the power consumption of the DMV is larger than that of the traditional voter. In order to reduce power consumption, we design a voter through an XOR gate and a MUX (Multiplexer), which consists of only12MOS transistors. As the DMV is a full fault tolerant low power voter, it can be used to substitute the top and all bottom voters in the TMR chip. Simulations in the different corners of CSMC0.5um process demonstrate that at least61%voter power consumption is saved by using DMV substituting three traditional voters. We use commercial software Siliconsmart to characterize the standard cell of the DMV for automatically inserting the DMV into the chip with EDA (Electronic Design Automation) tools. We have designed the ASIC based on DMV in CSMC0.5um process. Test results show that the power consumption of the self-refresh TMR ASIC based DMV is only0.486mA, which is conforms to the requirement (0.7mA). While keeping other performance same, the balise using the TMR ASIC based DMV has better performance in the power and start time than that of the Siemens production. The research result of DMV has been published on SCI journal IEICE Electronics Express, Vol.11, No.4(2014.2).