Tiled Stream Processor Architecture

The development of traditional processor architecture is restricted by many problems arose in nanometer technology designs, such as power dissipation, wire delay, design complexity, etc. Tiled processor architecture is a potential solution to these challenges. Tile stream processor is an architecuter for compute-intensive application. Tile stream processor can utilize plentiful but cheap transistor resources introduced by Moore's Law and become scalable. Tiled design method organizes computation, storage and interconnects resources into basic tiled architectural units, which are relatively simple, distributed and reusable. A high-productivity processor can be composed of plenty of such tiled units, interconnected by highly efficient and scalable on-chip networks. The performance of tiled stream processor is determined by programming model, memory hierarchy, NoC (Networ-on-Chip) and computation model. Computation model, instruction set, architecture and mapping of stream programming model are studied in this dissertation. The major research contributions include:(1) Based on theory of dataflow-like computation model, single block multi data(SBMD) computation model is proposed which is used to organize comupatation resource of tiled stream processor. An instruction set which supports dataflow-like driven computation model is designed. SBMD indicates processing multi data in a super-block in which each data can be processed according to its data flow dependence. Control flow dependence of each data can be converted into data flow dependence by predicted execution which elimates transfer of control flow. Thus, each data can be processed in different control flow path. Explicit message passing is supported in SBMD model between loops in program.(2) A dataflow-like driven architecture for tiled stream processor called TPA-PD is designed. A data-flow driven computation model is employed for orginzing computational resource. To make use of data locality of applications, software-manage memory hierarchy is used. The tiled method is applied to TPA-PD in which several networks on chip are used to connect various resources.(3) Mapping of stream programming model is designed and implemented on TPA-PD. The StreamC/KernelC is a two-level programming language, which is stream programming model of TPA-PD. StreamC/KernelC is developed for Imagine processor. In order to run StreamC/KernelC program on TPA-PD, stream level translator and binary translator of kernel level are implemented. The infor of stream level instruction and binary microcode of kernel level on Imagine platform are translated by two level translator seperately. Code size of TPA-PD expands less than 2 times in average.(4) Experimental platform of TPA-PD is implemented. The effectiveness of dataflow-like computation model and architectural design is evaluated. The scalability of physical block resource, computational resource, network resource is discussed. The parameter setting of stream load/store unit is analyzed. The mechanism of optimizing execution time for single super-block is propsed. The schedule algorithm of instructions is studied to accelerate performance. Through experiment on simulator, it is found that not only architecture of TPA-PD is scalable, but also performance of TPA-PD exceeds stream processor in which computational resource is centralized controlled.