The Analysis Of Aggressive Execution Model On Tiled Processor Architecture

With the development of VLSI and further richer available on-chip resources, a new challenge in the research field of computer architecture is how to transform the increment of resources into actual promotion of computing power. However, the traditional architecture such as superscalar and VLIW is hard to scale,due to increasing wire delay and design complexity caused by the intrinsic characteristics, like centralized global control, data path based on broadcasting, etc. Tiled Processor Architecture (TPA) is proposed as a potent response to these problems. In the TPA model, instead of the traditional centralized global control, the policy of resource distributing and duplicating is adopted, and rather than broadcasting data path, point-to-point data transfer network is introduced, which evidently improves the scalability of processor. Nevertheless, in the sequential execution model on TPA, due to constraints of compiling technology and the application characteristics, it is quite difficult to fully exploit the ILP of applications. So we proposed an aggressive execution model for TPA. In this thesis, we analyze and evaluate the factors affect the effectiveness of the aggressive execution model on TPA in a method of combining theoretical analysis and experimental verification, and present some important instructions for the design of aggressive execution model on TPA.The research content and achievement include: (1) For the impact of control dependency on aggressive execution model, I propose the branch prediction technique at block level, and design predictor based on traditional branch prediction for it. Experiments show that control dependency has little effect on the aggressive execution model, and most applications achieve high precision in block-level prediction. (2) For the impact of data dependency on aggressive execution model, I propose the inter-block data forwarding and value-prediction technique, and define the concept of dependency depth. Experiments demonstrate that data dependency also show little impact to the model, either. (3) For the impact of structure dependency on the aggressive execution model, I evaluated all potential factors in structure, especially the topology of network. And again, the results show that structure dependency has almost no impact on the model and even promotes exploiting ILP with optimization.In summary, this thesis demonstrates that the aggressive execution model is feasible to enhance the tiled processor architecture, increasing the size of instruction issue window and further exploiting the instruction level parallelism, through multiple techniques to eliminate the control dependency, data dependency and structure dependency among blocks.