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Research On Stream Program Compilation And Optimization For Tiled Multi-core Processor

Posted on:2013-08-28Degree:MasterType:Thesis
Country:ChinaCandidate:M K QinFull Text:PDF
GTID:2248330392956221Subject:Computer application technology
Abstract/Summary:PDF Full Text Request
Tiled multi-core architectures have become an important kind of multi-core designsfor its good scalability and low power consumption. Dataflow Programming model as anefficient way to exploit the parallelism has been productively applied to multi-corearchitecture. However, while providing powerful computational ability, tiled multi-corearchitecture exposed the low-level details of multi-core to the programmers, like thehierarchy memory structure and exposed communication transportation, which presentsnew performance challenge for stream programming. Thus, to improve the efficiency ofthe execution of stream programming on tiled multi-core architecture, a systematic studyof stream compilation on tiled multi-core is needed.To overcome the difficulties on understanding and programming on Dataflowprogramming model, we design and implement the DFBrook dataflow programminglanguage and corresponding compilation system. DFBrook extends the gram of Clanguage and provide support for dataflow programming. The programmer couldembedded dataflow code in regular c code to specify the dataflow execution of theprogram. After the lexical and syntax analysis of the program we generate an intermediaterepresentation---synchronous dataflow graph. Then, combining with the characteristic ofthe target platform, we propose an efficient stream compilation framework for tiledmulticore architecture to optimize the execution of stream applications which is composedof three optimization strategies. Using the integer linear programming we construct arate-optimal software pipelining schedule to keep load balance. On this basis, a bufferallocation algorithm is proposed to allocate the data for pipelining schedule and redundantbuffer copy operation is eliminated. Meanwhile, the logical cores are mapped to thephysical cores to reduce the communication overhead. After the three optimizationstrategies, we generate the multithread code for the target multicore architecture. We choose Godson-T as the experiment platform and the common algorithms inmedia processing technology as the test programs and perform the experiment for differentoptimization strategy. The result shows that our compilation technology obtains greatimprovement.
Keywords/Search Tags:tiled multi-core, dataflow, software pipelining, communication
PDF Full Text Request
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