The Topology Study Of Low-Latency And Unbuffered On-Chip Network With Separation Of Transmission And Control

The advanced technologies have improved transistors switching rate, and reduced transistor gate delay. However, signal transmission and power consumption are getting worse due with the global wire delay. And furthermore, currently microprocessor architecture determines the chip wires should be connected to every memory and function logic unit. The widening gap between the relative of gate speed and global wire delay will have a serious impact on microarchitecture performances. Facing the increasing of the number of embeddable microprocessors and special logic modules, the current microprocessor architecture might own insufficient ability to deal with demands for the multi-core chip systems. An ideal alternative architecture for these challenges and demands is Network on-Chip (NoC) based on pipeline method. It could convert the unpredictability of the global wire delay into the predictable event latency. The system architecture based on NoC that changes system method from computation-centered to communication-centered. And what its key goal of on-chip network is to construct a high-performance on-chip communication network with low-latency, and scalability for multi-core chip system.At present, the major NoC topologies include the mesh structure, tree structure, and multi-ring structure. As a new type of research fields on the cutting edge of science, there are many interesting research topics in NoC fields, such as system architecture, service applications, system design platforms etc. However, NoC architectures have inherited some weak points from the computer communication network, e.g. EDA tools, operation system, cost, latency, buffer strategy, network congestion, deadlock, and network hot spots and other issues. Due to the fact that the switch node as the primitive element in the current NoC architectures should be needed to finish all missions except physical layer functions.In brief, we present a new type of NoC topology named as S-mesh. It is an on-chip network with the separation of control and transmission. In the S-mesh system, the kernel communication network adopts circuit switching mode, and the edge devices, such as resource nodes, adopt the packet switching mode. The S-mesh network architecture consists of two types of sub-networks: mesh-based data transmission network and butterfly-based control networks. There are two unique characteristics. One is that functions of switch nodes only undertake link layer functions and physical layer functions. Another is that the new control units added would be responsible for the system resource management, routing decisions, and flow control. The main study of this thesis mainly embody in several aspects, such as network topology, unbuffered switch microarchitecture, network flow control mechanism , and system routing algorithm, etc.In the first place, the S-mesh architecture designed as separation of transmission and control to optimize the switch node's functions, and to construct lower-latency on-chip communication network. Secondly, the unbuffered switch node architecture can effectively reduce the chip cost. And the packets latency in each switch node would be reduced to one clock cycle. Thirdly, the routing algorithm of S-mesh based on the shortest routing algorithm destination-oriented routing algorithm is designed to make optimum transmission paths. It works with three-level flow control strategy to make the system immunizing for network congestion and deadlock. In the last place, BS-mesh network architecture based on bypass network optimizes the adjacent nodes communication performance in the S-mesh architecture.The results shown that control network in S-mesh has strong ability to handle numerous transmission processes. Its peak performance is approximately 2425 MIPS. The S-mesh architecture has immunities on network congestion and deadlock. The unbuffered architecture of switch node can reduce system cost. Meanwhile its bandwidth can achieve approximate 23.5GB/s. The bisection bandwidth of the 4×4 S-mesh network is up to 37.64GB/s. It has obvious advantages on switch area (0.0186mm~2 ) and higher operating speed.The S-mesh network architecture possesses a few characteristics of low-latency, high-performance, and low-cost. It is suitable for medium-scale and large-scale on-chip network, especially for services with long packet length. Meanwhile, the BS-mesh network architecture is suitable for data transmission which is locality effect.