Architecture Of Accelerators For Remote Sensing Image Processing Algorithms

With the rapid development of remote sensing technology towards high spatialresolution, high frequency resolution and high spectral resolution, the size of remotesensing images grows significantly. To meet the requirement of processing massiveremote sensing data realtimely, more and more image processing algorithms are be-ing migrated from ground computing to on-board computing. The wavelet-basedremote image processing algorithms have become most popular because of the ex-cellent features of wavelet transform. And on-board computing requires low powerconsumption, small size and powerful computational capabilities. Therefore, it's ofgreat significance to study on specific accelerators for kinds of remote sensing imageprocessing algorithms.Firstly, a comprehensive investigation is developed on popular remote sensingimage processing algorithms. And based on the di?erent features of memory ac-cess, they are classified into three categories - regular-window-access algorithms,bit-access algorithms and irregular-window-access algorithms. For each category,the computation and memory requirements are analyzed.An optimized 2×2 array archtecture for lifting-based two dimension discretewavelet transform (2D-DWT) is proposed specifically because wavelet transformis the foundation of this research. The proposal is composed of two row proces-sor (RP) which operate on di?erent rows and two column processor (CP) whichoperate on di?erent columns. It exploits the parallelisms between di?erent rowtransforms, between di?erent column transforms, and between row transform andcolumn transform to improve the excution speed. Because the array can coincidewith the computation of 2D-DWT, the data produced by RPs can be consumed byCPs in time. The bu?er between RPs and CPs are also reduced.For the algorithms with regular-window-access type, a scalable multi-data-windows-parallel architecture is proposed in which a three-level memory hierarchyis employed. Compared with other related works, our architecture can not onlysupport the window access pattern to memory, but also support the data reusabilitybetween multiple data windows. And also the scalability of proposed architecture isdicussed based on the balance of the computing requirements and available memory bandwidth.As a typical bit-access algorithm, the embedded block coding with optimaltruncation (EBCOT) algorithm in JPEG2000 standard is composed of bit-planeencoder (BPE) and arithmetic encoder (AE). A subblock-based BPE scheme is pro-posed firstly to conquer the mismatch in memory access caused by the traditionalscheme. And also, the new scheme makes it possible to encode multiple subblockparallelly. Based on the subblock-based scheme, a subblock-based BPE architectureis proposed in which subblock-parallel and sample-parallel policies are employed.The architecture not only improves the encoding speed, but also reduces the re-quirements for on-chip memory. For the AE part, a single-symbol coding three-stagepipeline architecture is proposed after an investigation of several popular pipelines.And also the interface between BPE and AE is discussed to balance the di?erencein speed.Finally, the wavelet-based automated global remote sensing image registration(WAGIR) is taken as an example to study the accelerator architecture for irregular-window-access algorithm. The resampling process and the computation of corre-lation coe?cient are the kernels of WAGIR. So the WAGIR is accelerated by ac-celerating the resampling and computation of correlation coe?cient. Traditionalresampling process demands great on-chip memories, and cannot be implemented inhardware e?ciently because of the irregular sliding of data window in the referenceimage. A block resampling algorithm is proposed to address this problem. In thenew algorithm, the result image is resampled block by block to reduce the scopeof required data. Based on this scheme, a BWAGIR (block WAGIR) architectureis proposed in which pipelining, parallel resampling and computation of correla-tion coe?cient, parallel memory access, and parallel multiple BWAGIR modulesare employed.