Research On The Acceleration Policy Of Software Based Micro-architecture Simulation

Micro-architects explore a vast design space to identify the best processor designs. To evaluate the design alternatives, Micro-architects rely on the cycle level micro-architecture simulators. However, the simulation speed is a bottleneck in this design exploration because the simulation speed of existing simulators is extremely slow. What's worse, the simulation of multi-core and many-core architecture is becoming more and more complicated and this leads to problems with slow simulation further exacerbated. Hence, it is urgently necessary to study on acceleration strategies of micro-architecture simulation.It is an effective way to speed up simulation rate by only detailed simulating partial dynamic instructions of a benchmark's full dynamic instruction stream. However, there are two key challenges: (1) how to select instructions for detailed simulation, which is named as instruction selection problem; (2) how to warm up micro-architecture states before detailed simulation, which is named as warm up problem. These two problems are for the sake of a common goal which tries to accelerate simulation rate as much as possible under a given simulation accuracy.The Two-Stage Systematic Sampling simulation strategy is proposed to sovle the instruction selection problem. Traditional sampling methods either treat every dynamic instruction segment as the same causing to simulate redundant instructions in detail or try to capture the periodic behaviors strictly but difficult to achieve desire result. Two-Stage Systematic Sampling simulation approach selects the instructions for detail simulation in two steps: (1) Divide the full dynamic instruction stream of a benchmark into large segments which have the same length and apply systematic sampling to select many segments as the candidate detail simulation instructions. (2) Divide every selected segment in step 1 into smaller segments and apply the same sampling strategy as the step 1 to sample many segments as the final detail simulation instructions. This approach can reduce the redundancy caused by treating every instruction segment as the same and can also be evolved to several other sampling simulation approaches such as systematic sampling and stratified sampling simulation. The simulator using Two-Stage Sampling (TSSS) approach can also be used as a program behavior analysis tool. The experiments show that this approach can obtain 15% acceleration over the famous SMARTS approach while they have the same precision level.The Cantor simulation strategy employs an unconventional approach to sovle the instructon selection problem. It applies the fractal theory in micro-architecture simulation. It selects the instructions for detail simulation according to the construction procedure of trisection cantor set. Since the cantor set has the cluster property, it can be used to simulate the same cluster property of program behaviors. This thesis constructs a model for determining the number of divisions based on experiment observations. After this single parameter's determination, users can simulate benchmarks simply. The Cantor simulation approach harvest 23% speedup over SMARTS approach but lose precision slightly. This approach can be used as a complement for other simulation methods.The acceleration strategy of functional warm up aims to resolve the warm up problem. Since the micro-architecture states are not recorded before the detail simulation, the simulation results may not reflect the real behavior of hardware. Systematic sampling function-warming is suggested by this thesis and it is based on the fact that the states of large hardware structures often have a long history. The experience model for determining sampling parameters is also provided in this thesis. Experimental results show that the proposed strategy can speed up simulation rate of 27.8% while the accuracy is reduced marginally.The multi-core and many-core architectures are becoming a new trend in micro-processor area, yet the simulation of them is more challengeable than that of single-core processors. The strategies studied in this thesis can be applied in simulation of multi-core architectures. Meanwhile, this thesis studied on the possible models of multi-core architecture and the simulation of them.