Research On Network Processors Parallel Processing And Congestion Control Mechanisms In The High Performance Router

In recent years, new network applications and protocols as well as the link bandwidth requirements grow rapidly, higher performance and scalability are required for next generation high performance routers. However, the traditional routers cannot meet the requirements mentioned above. Therefore network processors-based high performance routers have attracted much attention because of their higher performance, flexibility and scalability.The performance of a network processors-based high performance router mainly depends on three factors: 1) .the inherent performance of network processors used in the router; 2). the organization and employment of network processors in router systems; 3). the related control algorithms of QoS. Carrying on research work around the three factors mentioned above is very important to improve the performance of network processors-based high performance routers.This dissertation focuses on the three factors related to the performance of network processors-based routers. It includes: 1).the performance of parallel multithreads; 2).the dynamic load balance algorithm for high speed packet forwarding system composed of the parallel network processors; 3).the congestion control mechanisms fit for parallel network processors. It is important for designing network processors-based high performance routers.The performance of network processors has a significant impact on the performance of routers, while the performance of network processors mainly depends on the parallel processing mechanisms. Network processors parallel performance model (NP~3M) and network processors Multithread Parallel Processing Time Model are constructed in the dissertation, and these models are verified by experiments. Furthermore, the characteristics of multithread halting and the cost of multithread switching are studied, and the results are verified by experiments. The results of the research have been used to guide the design of network processors picocode of the important "863" project and to improve the processing efficiency of picocode software.Parallel data processing between network processors is an efficient way to improve the performance of routers. In this paper, we conduct research on load balance and packets order preserving problems which are induced from parallel processing of network processors, propose and design D-IHDA, a dynamic load balance algorithm orienting packet traffic characteristics, D-IHDA introduces a dynamic judging mechanism for maximum traffic and defines the probabilistic algorithm for updating mapped entries according to different traffic characteristics. We propose the idea for traffic control algorithm which can be used in aggregate network processor models, and introduce the twice-distributing mechanism to improve the system performance and further reduce the packet loss rate. The simulation results show that this algorithm with the well-chosen design parameters has better overall performance on its expansibility, load balancing and packet ordering compared with other algorithms.QoS controls algorithms are very important to the performance of routers. Through analysis of the data packet processing flow of network processors, we induce the multistage congestion control mechanism. Furthermore, to solve the problem of isolation between the congestion control mechanisms in different congestion control stage, we propose CC-AMR, a congestion control mechanism with awareness of multistage resources, which can synthetically utilize some resource congestion information to manage the buffer of network processors and aviod congestion. We improved the performance of routers by applying this mechanism in the important project of National High-Tech Research (863) Program.In order to reduce average queue length and alleviate wobble problem, a buffer management algorithm called A-SARED based on the relationship of packet flow input rate and buffer occupancy percentage is proposed. Compared with RED and SARED, it has shorter average queue length as well as improved throughput. Contraposed to traditional mechanism poorly supporting QoS, we design a DiffServ-oriented buffer management and packet schedule mechanism called CCAAQM and the corresponding implementation algorithms. The simulation results demonstrate that CCAAQM mechanism can provide differentiated service for flows that need assurable service within network node.The work of the dissertation is supported by the important project of National Science Foundation of China (NSFC) and the important project of National High-Tech Research (863) Program. The major results are successfully applied in developing the "New Generation Internet High Performance Router". This project gained the Second prize of National Scientific and Technological Progress Award in 2006.