Design And Verification Of Low Power And High Performance Graphics Controller

With the rapid development of science and technology, a display technology revolution occurs. Especially with the advancement of internet and IT industry, knowledge, information dissemination and immediate communication relies more and more on display technology. As a result, display device has become the principal means for exchange of global, real-time information. The great progress of communications technology and handheld devices promotes the graphic display technology of small/medium scale, requires graphics controller be more powerful and effective. There are two main aspects as follow: in order to extend the working hours of battery, the graphics controller should be low power-consumed. On the other hand, with the popularity of color screen, which leads to an increasing volume of display data, not only the functions to produce colors but also different graphics acceleration engines are required.Through the research on the theory and methods of small/medium scale graphic display, a novel graphics controller with low power-consumed, integrated multiple graphics engines and high-performance color production circuits is designed.First, based on the analysis of timing models of dynamic LCD driver, display mode and memory structure, MCU interface standard and LCD interface standard, a architecture of high-performance graphics controller with integrated multiple graphics acceleration engines, a variety of MCU interface and display interface and embedded frame buffer is designed. From two aspects of the performance and power consumption, optimal design on the circuit structure of a central control unit has been done.Second, based on the analysis of the principles of various graphics acceleration engines such as hardware rotation, picture-in-picture, ink layer display, and virtual display and so on, the relationship between scanning position (X, Y) and the address of frame buffer is found. Then the mathematical model and hardware realization can be deduced. On the base of analyzing the respective characteristics of spatial dithering algorithm and temporal dithering algorithm, the method used in the design to gain the gray and color is put forward. In addition, according to the block effect in the spatial dithering algorithm and the flicker caused by temporal dithering algorithm, the improved methods are put forward respectively.Moreover, verification and back-end design of the chip including functional verification, formal verification, FPGA verification, memory built-in-self-repair, low power design and layout design are completed. Finally, functional test and power analysis of the sample chip have been finished. Functional test result shows that circuit function of the chip is completely correct and that memory's clock frequency is up to 70MHz and completely satisfies the design requirements, while the result of power analysis shows that the chip has very low power consumption and high application flexibility.