Concatenated Coding Techniques And Implementation Research For Optical Fiber Communications

Forward error correcting techniques (FEC) has become one of the key techniques in high-speed and long distance optic-fiber communications. The use of RS(255,239) codes recommended in ITU-T G.709/975 can effectively improve transmission quality, reduce system cost, which also be referred as standard FEC. With the development of optic-fiber communications, the super FEC, which has a highercorrection ability than RS(255,239) code, are required,and the concatenated codes which consist of RS and BCH code due to its higher coding gain and moderate complexity have become a focal point of research. Some high-performance super FEC have been theoretically analyzed by many researchers. The main difficulties of concatenated codes for practical applications in optic-fiber communications are how to design and implement high-performance FEC chips with a low complexity and a high speed.This thesis devotes to the research of high-performance concatenated code techniques in optic-fiber communications and focuses on the design of low-complexity and highspeed VLSI architectures for RS and BCH codes. The optimization strategies in system level and the algorithm's implementation structure were employed to reduce the complexity of the codes and the parallel processing and pipelining techniques were used to speed up the throughput.Among three major building blocks in the RS decoder, i.e., syndrome generator unit, key equations solver and the Chien's search, the key equations solver block is the throughout bottleneck and the most area consuming unit. This thesis investigated the implementation of the modified Euclidean (ME) algorithm which was extensively used in RS decoder and proposed a low complexity structure of ME algorithm by using pipelining technique and multiplexing finite field multiplier. A 2.5Gb/s RS(255,239) decoder has been designed and implemented with proposed structure, and it can be used as the standard FEC recommended in ITU-T G.709/975 and also as outer codes of concatenated code designed in this work.A hardware solution established for binary BCH codes is the serial Linear Feedback Shift Register (LFSR). In some situations, such as high-speed optical communications, a parallel BCH encoder with which multiple bits are handled simultaneously is necessary. Accordingly, a parallel BCH decoder is also desirable. The thesis studied the parallel algorithm and architecture of a BCH encoder. With the proposed algorithm, the BCH (2184, 2040) encoder with 8-bit parallelism was realized. It could achieve the data rate of 2.5 Gb/s. The advantages of the algorithm were that it could effectively eliminate the effect of large fan-out in the parallel BCH encoder by using a tree-type structure, sharing sub-expression, limiting its maximum number and balancing load technique.The optimization of the parallel BCH decoder could be easily accomplished by using the unique characteristic of binary BCH codes. Firstly, simple square circuit and higher power computation circuits for finite field were designed to realize the low complexity parallel syndrome computation circuits. Secondly,...