Performance Analysis And Optimizations Of Microprocessors

With the ever-increasing design complexity and limited design time, it is a question for each designer: how to efficiently perform analysis and optimizations of the target system? This paper tries to answer this question via studies of the performance analysis environment and the methodology needed by a realistic high performance microprocessor (the godson-2 processor [HZL05]) design.At the core of performance analysis environment are the models of target processors and workloads. Accuracy, speed and flexibility are the key requirements of these models. RTL models dictate the logic behavior of microprocessors, but they are too slow, and baring too much details to be flexible enough. This thesis proposes a way to model hardware in high level programming languages and successfully uses it to build a signal-level simulator, which is called ICT-godson. ICT-godson has the same logic behavior with the Godson-2 RTL model, but it can run 10x faster.ICT-godson partially solves the speed problem, but since it bears all the details it is still limited in flexibility. We go further to build a more high-level model, which is called Sim-godson. Sim-godson is a performance model of the godson-2 processor written in C. The adoption of execution-driven organization, highly efficient data structures and algorithms, and modular design ensures its speed and flexibility. Sim-godson can simulate around 500K cycles per second and this is comparable to the fastest public detailed simulators. Sim-godson supports fast evaluation of large workloads. It can accurately predict the performance of SPEC CPU2000 in an hour. Sim-godson supports both user mode simulation and full-system simulation so that we can choose a conventional mode for different purposes. And this is also useful for isolating the effect of the operating system and extern I/O. We establish a systematical validation flow for Sim-godson, which is effective in controlling the model error.To best meet the requirements of different design stages and design purposes, a performance analysis environment should be composed of a set of tools. Besides ICT-godson and Sim-godson, the environment established by this thesis includes the RTL model and FPGA emulation platform, and some other software tools. RTL and FPGA are used to validate high-level models while software tools are used for tasks such as workload analysis.This thesis implements a multi-facet data collection scheme in both ICT-godson and Sim-godson. They can present different views of target processor's behaviors and help designer to find bottlenecks. To better understanding the behavior of high-performance microprocessors, we further investigate several methods for bottleneck analysis. These methods can systematically decide the effects each bottleneck and their interactions have on the performance.