Researches On Architectures Of Still Image Coder

Embedded wavelet coding technique is a main method for image coding. Especially SPIHT (Set Partitioning in Hierarchical Trees) and EBCOT (Embedded Block Coding with Optimized Truncation) are two very important algorithms. Because of good restored image and random access for coding stream, these algorithms become the first choices in practice. With increasing requirements for image coding in many application fields, especially in military application aspects such as satellite surveillance etc, these excellent algorithms must be implemented in hardware urgently.In the image coding field, the design of high performance image coder is always the goal that many relative researchers pursue. As for performance, low memory, low power and real time processing are hot points in research. In the paper, author studies the design of image coder in deep, especially places emphasizes on implemental architectures of coding algorithm with high efficiency and performance. The paper presents creatively implementation architectures with low computation and memory for real-time processing. The proposed architectures have been applied to real coding system successfully. The followings are main content of this paper:1. A VLSI architecture of line-based real-time lifting discrete wavelet transforms. The architecture processes horizontal filtering and vertical filtering simultaneously in 2-D transform using synmtery boundary. The transform time for one image equals to one image transmission time that is 2.6 times faster than traditional method. For reducing memory requirement, the architecture only uses and schedules internal buffer without external buffer.2. An efficient architecture composed of bit plane-parallel and pass-parallel coder for EBCOT entropy encoder. After the detailed analysis of EBCOT algorithm, the coding information of each bit plane and the corresponding passes can be obtained simultaneously. Therefore, bit plane-parallel and pass-parallel coding (BPPP) is proposed, and its VLSI architecture is shown in details.3. A bit plane-parallel architecture for a modified SPIHT algorithm using depth-first search bit stream processing. In the architecture, the coding information of each bit plane can be obtained simultaneously. The coefficient tree is traveled by depth-first search manner Then, the corresponding VLSI architecture to implement the formulated requirements is presented.4. A low complex compression algorithm for spectrum image and its hardwaresystem. The system has been applied to the moon exploration plan, and passed first stage test.5. The JPEG2000 standard hardware coder for satellite image trassmission. The coder uses BPPP architecture for EBCOT mentioned above to reduce processing time. And a common net interface is implemented in coder for data exchange with external network.