| With ten years development, the industrialization of the first generation digital satellite television broadcasting with DVB-S and MPEG2 has been matured, which has being adopting by the most of the countries in the world. Though the throughput of satellite set-top box is very large in CHINA, the industrialization of the corresponding IC is just beginning. With the proclamation of the new generation digital satellite TV broadcasting standard-DVB-S2, the new market goes into the gestation period.Taking the pivotal chips in digital satellite STB as the research objects, the author analyzed and studied the algorithm and SOC architecture in DVB-S, DVB-S2 demodulator and mpeg decoder, and proposed some optimum algorithms and realization structures, which DVB-S and SOC related have been verified by ASIC and mass production, and which DVB-S2 related has been verified on FPGA.The main contents of this paper are as follows:The first chapter introducts the standard of digital satellite TV broadcasting and source standard, also the status quo of the technique and industrialization of digital satellite TV broadcasting in the world and CHINA, then it lists the structure and the main contribution of this paper.The second chapter first provides the satellite channel model. Then taking the DVB-S demodulator algorithm as the research object, the author analyzed the algorithm of the timing recovery, carrier recovery and equalization, and proposed a demodulator architecture which is be propitious to AISC realization. The result of instrument test and the comparision with other mainstream DVB-S demodulator chips indicated that the new architecture and algorithm exceeds the competitor on the performance of receiving the real signals.Taking DVB-S2 as the research object, the third chapter analyzed the algorithm of the timing recovery, physical frame synchronization and the carrier and phase recovery, and proposed the demodulator scheme in broadcast services mode and interactive services mode. First the author proposed a DVB-S2 demodulator algorithm architecture in broadcast services mode propitious to AISC realization, which can capture the signal fleetly in pilot-less mode. According to the feature of large carrier frequency error, a timing lock detector assistanted carrier sweep algorithm was proposed, which improved the speed of carrier sweep in low symbol rate. A DVB-S2 physical frame synchronization algorithm was introduced, which improved the speed of physical frame synchronization. Also a carrier coarse estimation algorithm was proposed, which improved the speed of the carrier coarse estimation in low symbol rate. Then analyzed the disadvantage of the existing algorithm, a DVB-S2 demodulator algorithm architecture in interactive services mode propitious to AISC realization was proposed, which was satisfied with the low SNR performance requirement. Meanwhile a cascaded carrier and phase recovery algorithm was proposed, which is high speed.Taking the blind search algorithm in DVB-S as the research object, the fourth chapter analyzed some existing algorithms of symbol rate blind estimation, and improved the symbol rate blind estimation algorithm based on the baseband shape pulse. Then a planar blind search algorithm based on frequency domain and time domain, which can autoscan all the frequency point and symbol rate. In the algorithm, one coarse estimation algorithm of symbol rate and carrier frequency based on frequency domain and two fine scan algorithm of symbol rate based on time domain are included. All above algorithms are verified by mass production.Taking the SOC design of DVB-S demodulator and MPEG2 decoder as the research object, the fifth chapter provided the SOC design flow which faced to the industrialization. Then analyzed the SOC bus architecture and stream design, and provided the chip realization architecture. Meanwhile it proposed the realization scheme of modules. The communication mechanism inter-processor in SOC was proposed. This architecture was verified by ASIC and mass production.
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