VLSI Design Of DVB-C Baseband Chip

DVB-C has been the national standard of digital Cable TV in our country. With stepping into HDTV era from analog TV, the increasingly requirement of demodulator chips with high performance is evident. The VLSI design of demodulator chip has become one of the focuses of academic and industrial research.Since coaxial-cable is the transmission media, Quadrature Amplitude Modulation, which works well in the invirenment of high signal to noise ratio, is used in DVB-C standard, and DVB-C baseband chip is subsequently a wide-band QAM demodulator. QAM modem has been widely used in telephone channel, and researches now focus on the area of wide-band communication with high data rate. Although there are many productions in these years, we also face to a number of unresolved technology difficulties.As Cable TV net is a typical broadcast net, transmitters can not provide training sequence to users that probably connect in momentarily, and there is no information with previous knowledge in transmission content. So blind receiving is one of the key problems of this dissertation. With the great progress of IC technology, scale of chips and complexity of design are keeping increase. Verification becomes one of the most difficult and challenging problem in IC design, and becomes the key factor in design periods.This dissertation focuses on DVB-C baseband chip design, but not limited on it. Common problems of design and verification in QAM demodulators are solved by doing research on synchronization, equalization and other key techniques in QAM demodulation and large amount of verification work. The productions can be implemented in HDTV, cable modem, satellite, micro wave communication et al that based on QAM, and give direction and reference to communication base-band chip design. The main contribution of this dissertation can be concluded as following:1, Based on studies of DVB-C standard, the idea of blind receiver is applied in system design, discusses algorithm choices and unresolved problems in current research, makes some analysis with trade off between performance and realization in stage of system design.2, Timing recovery loop with Gardner algorithm is discussed in detail, and method of improving performance is given. Some design methods of interpolation filters are proposed and performance of Lagrange interpolation is analyzed.3, By doing analysis on phase detect algorithm based on decision direct, some improvement of extending acquisition range and reducing acquisition time is proposed, simulation results are given. There is also an introduction of direct digital frequency synthesis based on CORDIC algorithm.4, A review of blind equalization algorithm based on stochastic gradient recursion is proposed, and constant modulus algorithm that independent of carrier is mainly discussed. Comparison between linear and decision feedback, direct form and transpose form, symbol spaced and fractionally spaced equalizers is discussed and simulation results are given.5, Problems and solutions in mixed signal design are proposed. According to all-digital implementation scheme, this work proposes various optimization techniques to improve the performance of key modules, such as anti-aliasing filter, match filter and equalizer. Design results show that current optimizations guarantee the performance of the demodulator.6, By learning fixed point simulation and reference model techniques based on SystemC, this work proposes a reference model of cycle accurate level. Structure, flow and criteria of FPGA prototype verification system are discussed. Some specialties for verification of baseband chip are proposed, too.