Two-path Bandpass ∑△ Modulator Design

Oversampled bandpass A/D converters based on sigma-delta (@) modulation can be used to robustly digitize the narrowband intermediate frequency signals that arise in radios and cellular systems. Digitization of the IF processing confers several important advantages in a receiver, including greater reliability, potentially lower power dissipation. Moreover, it is suitable for system-on-chip (SOC) integration of radio frequency (RF) systemes with the multi-mode potential.The implementation of a high-speed bandpass @ modulator that achieves large dynamic range of 80-dB for 200kHz narrowband IF-signal digitization with power consumption of about 20-mW involves significant challenges that are explored in this research. This dissertation describes a new two-path architecture for a fourth-order bandpass ∑△ modulator that is more tolerant of analog circuit limitations at high sampling speeds than the other implementations based on the use of two-path architecture. Comparative analysis proves the bandpass SA modulator described in this paper has several advantages such as lower power consumption, lower two-path mismatch and smaller chip area.An experimental prototype employing the two-path topology has been integrated in a 0.18um, single-poly, six-metal CMOS technology with MIM capacitors. The interleaved paths clocked at 40MHz that means the effective sampling frequency of 80MHz digitize a 200kHz bandwidth signal centered at 20MHz with 80dB dynamic range and power consumption of 18mW while the core chip area is 0.45mm2. To achieve such objectives, circuits such as bootrapped sampling-switch, two-stage amplifier and comparator, feature the characteristics of low-voltage structure and high SNR. An analysis of noise in the experimental prototype reveals that its inband noise floor is dominated by a combination of amplifier noise and thermal noise from switches, which predicts the dynamic range of 81.3dB.Nonideal effects relating to this new two-path architecture, such as thermal noise, path mismatch, timing jitter, finite amplifier gain and settling time are described and analyzed with great convenience offered by methodology described in this dissertation, which is transferred from analysis of integrator in lowpass SAmodulator. A systematical TOP-DOWN design flow with the optimization with SNR and power consumption for two-path bandpass ∑△ modulator has been concluded.