Research On Audio Coding/Decoding Algorithm And Hardware/Software Codesign

AAC is a kind of high-quality audio coding standard and it is none back compatible part of MPEG-2 audio standard. It is also the kernel of MPEG-4 audio standard. In this dissertation, psychoacoustic models filter banks quantization and bit allocation predicate coding and temporary noise shaping is analyzed. On the basis of this introduction, some part of algorithm is improved. It includes: a new bit-allocation algorithm based on linear predication, that is to predicate the initial value used in bit-allocation procedure by the initial value of previous frame according to the correlation of the previous frame and the current frame. So the iterated loop number is reduced and the complexity of audio coding is reduced. Furthermore, on the analysis of the psychoacoustic models, some simplification can be made in the psychoacoustic models. The purpose of this simplification is to reduce the bit rate of audio stream.In this dissertation, the hardware/software co-design flow and AC3 decoding algorithm is analyzed and the AC3 audio decoding on the Virgo RISC-core. Then the extended instruction is added to lessen the CPU cycles used and to reduce the memory space used by the decoding program. That is, after decoding AC3 bit stream by software, the models are set up for the key sub-functions to get the extended instructions of RISC core and the key operation is mapped to special instructions. Next, the detail hardware of extended instruction is given. Finally, by using hardware/software co-evaluation method to calculate the memory space the CPU cycles used and the gates that the extended instruction added, the performance of the whole system is analyzed. Through this extension, the speed of AC3 decoding is fastened, the memory space is reduced and the gates of the whole system are lessened.In most of multimedia SOC (systems-on-chip), in order to maintain the real-time requirement, application program and data are stored in on-chip memory or Cache, it has the advantage of convenient execution and better performance. But large quantity of memory is often used and the area and power of the memory units usually hold the largest percentage of the whole chip. In this dissertation, some approaches are given to optimize the memory usage of SOC. Since the MPEG-2 decoding chip is a SOC, 32-bits embedded RISC CPU core is used to decode the AC3 and TS bit stream. The RISC core is also used to manage the different task in the chip and the video processing unit is realized in ASIC modules. In order to reduce the memory space of the system, AC3 program is optimized and hardware/software co-design method is used to optimize the memory space consumed in system level assemble level and hardware level.