Reliability Research On Electronic Packaging

The world information technology (IT) and electronics market was at 1.2 trillion dollars in 2000, making it the largest industries. The hardcore of integrated circuit (IC) is chip. Moreover, every IC has to be packaged before it can be used. The functions of an electronic package are to protect, power, and cool the microelectronic chips or components and provide electrical and mechanical connection of the microelectronic part to outside world. With the continuous improvements of IC integration, the electronic packaging became more and more important.The flip chip technology developed recently provides the shortest possible leads, lowest inductance, highest frequency, best noise control, highest packaging density, greatest number of inputs/outputs (I/0's) and lowest profile when compared with other popular interconnect technologies. It is expected, therefore, that flip-chip technology will become a mainstream technology in the future.The reliability of flip chip package was studied in this work by both experimental measurements and finite element simulations. The thesis is compased of five parts as following:1. According to the M1L-STD-883C standard of thermal cycle loading, the delamination propagation rates at the interface between chip and underfill were studied experimentally by using C-mode scanning acoustic microscope (C-SAM) for two types of flip chip packages with different states of solder joint. The report of determination for interface delamination propagation rate of real flip chip packages is hardly found up to now.2. The delamination at the interface is one of typical failure mode for electronic packaging. In order to get more understanding of the propagation behaviour of [he delamination, a series of finite element simulations related were done. Thestrain energy release rates G near crack tip under different conditions were calculated by employing three methods of the fracture mechanics (J-integral, straightforward method and crack tip opening displacement method). Then, the half-empirical Paris equation, which can be used as a design base of flip chip package reliability, have been determined from the crack propagation rates da/dn measured and the energy release rates G simulated. To our knowledge, for real flip chip packaging under the thermal loading, the Paris equation obtained from experiment da/dn and simulation G is firstly reported here, and will be useful practically.3. A new method for calculating the strain energy release rate of delamination crack propagation at an interface between dissimlar materials was suggested by using the J-integral with a small flat rectangular contour near the crack tip. It was verified in this work that the J-integral with a special flat rectangular contour near the crack tip can be used as the energy release rate at the interface between chip and underfill. Because the calculation of J-integral is much simpler than other method, and the multilayers and interfaces are ubiquitous in microelectronic packaging structures, it is expected that this method will be widely used in the calculation of the strain energy release rate in high density electrical packaging, especially.4. A new level of electronic package design is developing to fulfill the requirement of high density electronic packaging technology. Recently, a new research field, design technology and design tools, is taking shape with the developing of electronic packaging technology. In order to minimize time to market and product development cycle, the next generation must be achieved. Unfortunately, there lack systematic and comprehensive reports on this new field. In this thesis, the design concept and methodology, design standard, and the general program of measurement, simulation and automatically design are all described in detail based on electrical, thermal and mechanical design in electronic packaging for qualification of product, optimization of design, and minimization of time to market.5. Based on ANSYS environment, the...