Study On Model And Method Of Effects On Performance Due To Process Variation In Nano-Scale MOS ICs

As feature size of semiconductor process is scaled to nano regime, silicon-based MOS integrated circuit (IC) manufacturing has become increasingly complex. This will make precise process control become increasingly difficult and result in the actual chip geometry, internal structure, working mechanism and characteristics parameters with a significant deviations from their design goals, which is called process parameters variation (PV) or process fluctuations. Furthermore, shrinking feature sizes with growing process variation makes the circuit performance degeneration and yield loss. So design for manufacturing (DFM) due to process variations has become a technical bottleneck and key challenge for today's nano-scale IC design and manufacturing.Firstly, an internal source of variation called random dopant fluctuations (RDF) in IC manufacturing with its probability density function is discussed in this article. Then a statistical model of simple expression of threshold voltage standard deviation induced by RDF and its probability density distribution function of the chip is presented. This method and obtained model are both simple and accurate. After that, changes of effective channel carrier mobilityμeff and parameters such as current gain factor p and the standard deviation of current mismatch are studied cause by RDF. After study on the theoretical basis of mathematical models and characteristics of existing models in detail, a simple, high accuracy and improved average drain current model called ALPHA law is found and applied in the article, thus a MOS current mismatch analytical model is achieved for a 65 nm process. At the same time, a simple, effective and accurate current mismatch model induced by RDF is derived based on this model.Variation of MOS current affects the accuracy, power, bandwidth and other performance of analog ICs and timing variability of digital ICs. A circuit simulation model for analog integrated circuits is presented considering PV due to RDF and an expression of different area and bias conditions of the circuit with a basic current mirror as a benchmark. The results show the impact on circuit performance for IC designers selecting different size and biasing condition in a specific process fluctuation. Average current model is reused to calculate standard deviation of an analytical model for digital circuit delay variability with a CMOS inverter as a benchmark, whose accuracy and reliability is verified by HSPICE Monte-Carlo simulations.Finally mathematical and statistical methods in analysis, design, optimization and control of IC process fluctuations includingσspace analysis, principal component analysis and response surface methodology is introduced. Then a robust design method for digital logical function base on neural network is proposed after combination of robust design methods in statistical design of experimental (DOE) and artificial neural networks. As long as appropriate expansion levels and values of the variables of factors, it is expected to application to optimization for IC design in process variation.