Dynamic Power Management On Many-core Systems

With the growing scale of high-performance computing(HPC) systems and improving performance, system power issues are also increasingly prominent. The huge system power, not only increases electricity bill and system operating costs,but also exacerbates the carbon foot-print and the pressure to the environment. The power issue highly constraints the performance scale of the HPC systems. Under this background, green computing has been attracting increasing research attention in both academia and industry. Energy-efficiency design has become one of the primary design requirements of HPC systems. On the other hand, many-core architectures are playing a more and more important role in the HPC area, boosting the system performance, meanwhile consuming most of the system power. Thus, research of dynamic power management(DPM) for many-core systems, reducing the power consumption and improving the energy efficiency, has substantial significance for improving the energy efficiency of the entire computing system.Considering the new features of many-core architectures and the urgent needs of their DPM, this work, studies the power modeling approaches for many-core architectures, explores the flexible and scalable DPM technologies of many-core architectures, and studies the efficient dynamic voltage and frequency scaling(DVFS)technology for many-core chips. The main contributions of this work are as follows:(1) Based on the characteristics of many-core architecture, we present an analytical power model for many-core chips based on performance monitoring counters(PMCs). The model takes into account both of power settings and program execution patterns to promise the modeling accuracy. Through experimental analysis on the Intel SCC, we verified the predictive accuracy of the model under DVFS.Meanwhile, experimental results show that the model outperforms other many-core power models.(2) We present a flexible and scalable power management solution for manycore systems, Powe Rock. In Powe Rock, we propose a lightweight profiling method for shared memory programs; Combining power and performance prediction model,Powe Rock can quickly obtain power control profile for guiding the optimal power settings towards the given power management goal; Considering the design feature of multiple voltage/frequency domains, we design a hierarchical domain-aware DVFS control mechanism, and implement a kernel-level scalable DVFS controller. PoweRock is implemented in Barrelfish operating system for evaluation of its efficiency,flexibility and scalability. Experimental evaluation results show that Powe Rock saves up to 65% of the energy consumption or EDP compared to the static DPM policy.(3) We study the DVFS delay characteristics in many-core systems with multiple voltage/frequency domains, and find the non-negligible DVFS latency in the Intel SCC. Based on this study and discovery, we propose a latency-aware DVFS control algorithm to avoid aggressive power state transitions and to improve the efficiency of DVFS. We implement this DVFS control algorithm in Barrelfish, and conduct the experimental evaluation on the SCC platform. Experimental results show that, compared to the baseline profile-guided DPM scheme, latency-aware DVFS algorithm obtains, in average, 15.2% improvement of execution performance,24.0% energy consumption and 31.3% EDP reduction. Moreover, our algorithm is also proved to outperform a prior DVFS approach attempted to mitigate the latency effects.