Research On Key Technologies Of High Reliability NoC

Conventional communication based on system bus fails to meet the requirements of complex So C in transmission rate, delay, scalability, global clock synchronization and reliability, a new on-chip communications structure is appealed to solve these problems, so the Network-on-chip(No C) is proposed. The traditional bus structure is replaced by packet switching and hierarchical method of No C approach to achieve the separation of processing element(PE) and communication structure(network), helps reduce design complexity, the power consumption is reduced effectively and the system performance is improved for the shorter communicate distance on-chip. Comparing with bus on-chip, No C has obvious advantages on scalability, reusability, predictability and customizability, it has become the inevitable choice for next generation of complex system architecture. At the same time, the deviation and vulnerability of large-scale integrated circuit chips become more obvious, the system fault rate greatly increases, these will affect the system performance and challenge the system reliability. In view of this, the large-scale digital integrated circuit must be capable of fault-tolerance both at circuit level and system level to improve the rate of final products, lower costs, and construct a stable, reliable, and performance- predictable system.Refering to the composition and research status of No C,an instensive study is made on No C mapping algorithm, topology and routing algorithm attempting to reduce the system power consumption and average network delay, increase the network throughput. A study of No C fault tolerant on layers of application layer and network layer also is made. The major researches and the findings are as follows:For the task scheduling and mapping, a new task model is designed and an optimized Particle Swarm Optimization(o PSO) is proposed to solve the problem that the traditional task model contains less information and the task scheduling algorithms based on that are inefficiency. The new model can reflect better the real inter-task relations, which includes the type of the task and its transfer cost, the type of PE and its running cost. After analyzing the requirement of task scheduling and mapping, the process is favorably divided into two situations: the task needs to run all the available PEs or not. A new method of coding and decoding is adopted, and the ways of updating key parameters are proposed, and overcomes the shortcomings of easily to be trapped in local optima in the prior period and poor local search capacity in the later period.For the No C topology,according to different requirements for network communication performance, a honeycomb-like topology is designed so that the topology is regular and easy to expend while the adjustable density of transmission roads could satisfy the varied requirements of different PEs, and the probability of congestion is reduced. The Doul-port NI is created so that every PE have at least two paths for receiving and sending data. The power consumption and latency are all reduced significantly, and the fault tolerance capability of No C and the system reliability are improved.For the No C routing algorithm, two parameters, the buffer occupancy rate and the number of packet transported are introduced, the adaptive fault tolerant routing algorithm that can be used to sense congestion in the system is designed. Routing nodes can well sense the failed routers, links and areas on the network and effectively work around the issues. The routing algorithm can also sense congestion of the network and adjust the transmission path adaptability.For the realization of No C. A tiny system is built on the platform of So CKit, and the function is verified by running a halftone algorithm.Through the study of the above key issues, effectively improve the network of multi-core system-on-chip to perform tasks at the application layer, network layer and physical layer efficiency, and the system reliability is improved. The works make positive guidance on the design and application based network on chip multi-core systems.