| Uncooled infrared detectors have been widely used in a lot of domains, such as military, border security, fire control, industrial inspection, traffic and etc. The performance requirements of the detectors are increasing as will. High performance detector chip requires high accuracy, high efficiency, large arrays, light weight and others.In this dissertation, many critical technologies have been investigated to obtain high performanced uncooled infrared detector chip based on integrated design, including the detector pixel model, the temperature compensation technology, the on-chip ADC technology, the non-uniformity compensation technology, and the detector array integration technology. The main contents are listed as follows.1. The integrated design model of microbolometer detector pixels has been researched which is electrical design platform compatible.An integrated design model of microbolometer has been proposed through mathematical deduction and parameter simulation. The difference of the output between the proposed and traditional models is less than 5% when the temperature is changed for 40 K.2. The temperature compensation technology has been discussed, including the self-heating effect compensation and the substrate temperature compensation.An on-chip current DAC or resistance DAC has been proposed to achieve the self-heating effect compensation. A compensation blind pixel has been added to the readout circuit to compensate the substrate temperature effect. One end of the compensation blind pixel is connected to the input port and the other end is connected to the output port of the amplifier as cross resistance for voltage biased readout circuit. While when one end of the compensation blind pixel is connected to the input port and the other end is connected to the ground, it works as integration resistance for current biased readout circuit. The proposed circuits are designed and implemented by using the integrated design model of micro bolometer. Samples with proposed temperature compensation technology work stablely when temperature is changed for 80 K during the test. The change of output is about 20% and the responsation rate changes about 40%.3. The on-chip ADC has also been studied, including chip level ADC and column level ADC.The performaces of on-chip ADC are determined using the integrated design simulation results, and then the chip level ADC and column level ADC are reserarched, respectively.The pipeline ADC has been researched as a kind of typical chip level ADCs. A power optimization software for pipeline ADC structure based on Matlab has been designed. With this software, two kinds of low power pipeline ADC structures were proposed. At the same time, two digital calibrations have been proposed based on the proposed pipeline ADC, one is a digital background calibration with dither injection and dynamic element match(DEM), and the other is a quasi real-time digital foreground calibration with both continuity and gain calibration. The two proposed calibrations have been applied to the proposed low power structures. From samples test, pipeline ADC with digital background calibration consumes 299.93 m W. Its DNL is +0.84LSB/-0.94 LSB and INL is +0.99 LSB /-1.19 LSB. Pipeline ADC with digital foreground consumes 280.96 m W with +0.86 LSB /-0.75 LSB DNL and +1.53 LSB /-1.41 LSB INL.The single slope ADC has been researched as a kind of typical column level ADCs. In order to improve the conversion rate of the single slope ADC, there are 3 kinds of methods proposed. They are half-cycle counting method, two-step comparison method and rows division method. To enhance the accuracy of the long-distance signal transmission on the detector chip, a current transmission method is proposed, too. The compensation blind pixel is used in the reference generation circuit in the single slope ADC, it is called as digital temperature compensation readout circuit. One sample of the single slope ADC consumes 21.86 m W with +0.72 LSB /-0.71 LSB DNL and +1.18 LSB /-1.09 LSB INL. Its consumption is about 290.19 m W when it is applied in 1280×1024 array chip. And the digital output changes 658 codes when substrate temperature is changed for 80 K. The change of output is 16.1% and the responsation rate changes 40.6%.4. The non-uniform compensation has been introduced too, especially for the three proposed readout circuits in this dissertation- the voltage biased readout circuit, the current biased readout circuit and the digital temperature compensation readout circuit.For the voltage biased readout circuit and the current biased readout circuit, an on-chip voltage DAC is proposed to achieve one-point temperature compensation. The proposed DAC could adjust the precision and range, and it contains of 4 kinds of voltage ranges. The FNP(Fixed Noise Pattern) of voltage biased readout circuit with the proposed DAC is reduced to 11.8m V. And the FNP of the current biased readout circuit with the proposed DAC is reduced to 10.4m V.For digital temperature copensation readout circuit, two DACs method is proposed to achieve two-point temperature compensation. The FNP of digital readout circuit with proposed method achieves 127.3m V.5. The detector array digital control technology is researched, containing array scan method, signal input method and signal output method.A 640×512 array infrared detector chip with voltage biased readout circuit and single slope ADCs has been fabricated and measured. The average responsation rate is 8.83 codes / K. Its RMS noise is 127.6μV, and the FPN noise is 14.5m V. The NETD of the sample is 62.33 mK.
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