Research On Performance-optimizing Methods For Control Flows And Variable Dual-voltage Technique In Reconfigurable Processors

Reconfigurable computing combines the flexibility of general-purpose computing and the high energy efficiency of application-specific computing. Its flexibility can reduce the design cost and time-to-market of a chip, and its high energy efficiency can relieve the power wall that general-purpose processors are facing. So, reconfigurable computing is following the trend of integrated circuit development and it will be an important direction of the future computing technology. However, reconfigurable computing also encounters many problems now: automatic compiler is a major challenge in flexibility; the significant gap between application-specific computing and reconfigurable computing is the major challenge in energy efficiency.This dissertation studies the framework of reconfigurable processors for the purpose of promoting the energy efficiency. The research is conducted in two directions: performance and power consumption. In the aspect of performance, the major problem of current reconfigurable systems is that control flows and control-intensive applications are becoming the bottleneck of the overall performance. So this dissertation concentrates on the design methods that improve the performance of control flows. In the aspect of power, one of the major problems baffling reconfigurable processors is the power consumption overhead caused by the large quantity of redundant resources and slack time in the circuit. So this dissertation concentrates on combining the techniques of power-gating and multiple voltage domains as well as improving them.This dissertation proposes several effective methods to improve reconfigurable processors in the above two specific directions. Parallel Condition technique increases the instruction-level parallelism of the predicated execution technique through designing fast control interconnections so that it can improve the performance of the conditional branches in control flows. Configuration Branch technique implements local configuration controller and thus it enables reconfigurable processors to handle the jobs that should be completed by the central processor. So the loops in control flows can be managed locally and efficiently. Compound Configuration technique designs fast data interconnections so the computation is completed fast in a combinational way. Meanwhile, it reduces reconfiguration time by merging those configurations of low resource-utilization into compound ones. Variable Dual-Volatge technique enables dynamic voltage scaling with applications on the basis of configurable dual-voltage technique so as to reduce even more power consumptions. The power model based dual-voltage design method belongs to compiling techniques. It cuts down the computation time spent on designing the variable voltage through building an ideal circuit-level power model.Combining the first three techniques proposed above, the reconfigurable processor can execute all types of control flows independently, and the performance of control-intensive applications can be improved by over 39% compared with state-of-the-art techniques, relieving the performance bottleneck caused by control flows. The other two techniques propose a framework of variable dual-voltage technique to reduce the power consumption of reconfigurable architecture. The dynamic power is cut down by 32% compared with single-voltage architecture, and by 15% compared with normal fixed dual-voltage architecture. Meanwhile, the fast voltage design method based on circuit-level power model can reduce the computation time of voltage design for variable dual-voltage by 100~10000 times. Overall, this dissertation proposes techniques that can improve the energy efficiency of reconfigurable processors effectively in all levels of its framework design.