Energy Efficient Architecture And Physical Attack Countermeasures For Reconfigurable Cryptographic Processors

Reconfigurable cryptographic processor is an application example of the reconfigurable computing concept to the cryptographic area.Compared to traditional ASIC(application specific integrated circuit)or ISAP(instruction set architecture processor)solutions,reconfigurable cryptographic processors can maintain the three requirements of cryptographic applications at the same time,i.e.,flexibility,energy efficiency(throughput/power)and security.However,there are still many open problems for the reconfigurable cryptographic processor design,which mainly fall into two aspects.On one hand,how to further improve the energy efficiency to bridge the gap between application-specific computing and reconfigurable computing while maintaining enough algorithm flexibility at the same time;on the other hand,how to increase the hardware security level represented by physical attack resistance utilizing the characteristics of reconfigurable computing style.Due to the fundamental significance of security to cryptographic applications,the later problem is even more important for reconfigurable cryptographic processors.This dissertation studies the architecture design methods of high energy efficient reconfigurable cryptographic processors and countermeasures against physical attacks.The research aims to explore new solutions of key technical points rather than cover all the details of processor design.As for the architecture design part,compared to the traditional design methods which pay more attention to the reconfigurable datapath,this research mainly focuses on the design of the reconfigurable controller which has a more significant influence on energy efficiency.Two strategies,i.e.,the Token-Driven Control Chain technique and the Configuration Context Layering and Compression technique,are proposed based on the characteristics of cryptographic algorithms to deal with the configuration control problem and the configuration context organization problem which seen as the major problems for the reconfigurable controller design.These two techniques can enhance the energy efficiency by increasing the computing resource utilization and reducing the configuration delay respectively.As for the countermeasure design against physical attacks,most of the current researches only focus on how to implement the mature countermeasures onto the reconfigurable architecture.This dissertation explores how to take advantage of the hardware architecture and computing paradigm of reconfigurable cryptographic processors to design new countermeasures.Based on the two fundamental properties of reconfigurable computing,i.e.,the dynamic and partial reconfigurability and the diverse computing resources,this research proposes two novel countermeasure solutions: randomized dynamic and partial reconfiguration against physical attacks and reconfigurable computing resource against physical attacks.Taking fault attacks which are becoming an emerging threat to reconfigurable cryptographic processors as the example,these two solutions are actually implemented by designing a series of specific countermeasures as well as security evaluation methods to against fault attacks.The two energy efficient architecture design methods proposed are implemented on a reconfigurable cryptographic chip.Compared to the state-of-art reconfigurable cryptographic processors,the proposed architecture achieves(average)16.5x higher energy efficiency.As for the physical attack countermeasures,the proposed methods can increase the fault attack resistance up to four orders of magnitude with the overhead controlled within 30%.What is more,the proposed countermeasures based on randomized dynamic and partial reconfiguration can also resist against novel double fault attacks as well as multiple fault attacks which can not be efficiently resisted by traditional countermeasures.