Key Technologies Research On Fully Integrated Satellite Navigation Receiver RF Chip

The global navigation satellite systems(GNSS), which is represented by global positioning system(GPS), GLONSS system, Galileo system, and Beidou system, are the cross fields of aviation, aerospace and information science. Nowadays, the satellite navigation systems play an essential role in both military and civilian fields. The single chip receiver can meet the demands of highly integrated, low power consumption and low cost, so it becomes the main implementation of the GNSS receiver. The radio frequency(RF) front-end circuit is the important part of the ground receiver, which decides the function and performance. With the performance improvement, the complementary metal oxide semiconductor(CMOS) becomes the most important technology of RF integrated circuit. So it is useful of the research on highly integrated single RF front-end chip of GNSS Receiver.According to the demands of satellite navigation receiver chip, the key technologies are studied in this dissertation, such as configurable low noise amplifier, image rejection mixer and filter, digital automatic gain control(AGC) and frequency synthesizer, etc. Based on the research, a demo-chip is designed, fabricated and tested. The main content of this dissertation is summarized as follows.Firstly, the low IF architecture is researched and selected for RF chip. Then, two methods are studied and proposed, one is the performance parameter calculation method suitable for receiver chip, another is the parameter decomposition method for module design. And a single-channel and a dual-channel multi-mode architecture are presented. All these are the foundation of the following research.Then, based on the classic architecture of cascode LNA with inductive degeneration, a dual-mode and a triple-mode configurable LNA is presented by using the switched capacitors. After circuit optimization and layout design, the configurable LNA is fabricated and tested. The measurement results show that the configurable LNA can work at 1.2GHz and 1.5GHz, the noise figure(NF) is 1.6~1.8dB, the gain achieves 16~20dB, the output 1dB compression point is more than-21 dB, the power consumption is 7~10mW.Secondly, the image rejection problem is studied. A quadrature active dual-balance mixer is proposed based on the traditional Gilbert architecture. A bypass current injection module is proposed to improve the performance. And then, a passive poly-phase filter(PPH) is studied, and a fourth-order PPH circuit is proposed, whose mismatch problem is solved by layout design after post-layout simulation. The complex band-pass filter is also studied for image rejection. A fifth-order complex band-pass filter is designed with frequency shift method. The image rejection rate is more than 30 dB with the mixer and filter.Thirdly, based on the Gaussian noise statistic characteristic of satellite navigation signal, a novel automatic gain control(AGC) loop is presented. The digitally controlled AGC loop occupies less area, and the gain adjustment procedure can be optimized to two-step, benefited from the accurate power estimation algorithm. The function and stability of the proposed feed-backward AGC loop is studied by establishing an AGC loop model. A digitally controlled programmable gain amplifier(PGA) is also proposed, which can provide 62 dB dynamic range with a 2dB gain step.And then, the phase locked loop(PLL) frequency synthesizer is studied to obtain a stable local oscillator(LO) signal. The “dead zone” problem and other non-ideality are solved by improving the frequency detector(PFD) and the charge pump. A LC voltage controlled oscillator(VCO) is designed to work in 2~3GHz. The high frequency divider is designed based on the source couple logic. Combinated with other modules and the off-chip loop filter, the PLL frequency synthesizer sub-system is fabricated and tested alone. The test results show that the PLL can be locked around 1.2GHz, and the VCO can be tuned from 2.23 GHz to 2.69 GHz. The phase noise is-101dBc/Hz@100kHz and-123dBc/Hz@1MHz.Finally, based on the research above, a fully integrated RF front-end demo-chip is designed and fabricated in TSMC 0.18μm CMOS technology. After planning the architecture, layout and pin, the chip is packaged in Quad Flat No-lead(QFN) package and tested. The measurement item includes all important parameter. The measurement results for Beidou B2/B3 show that the power consumption is 54 m W; and the total gain is 105 dB, the NF is 3.2~3.7dB, the 1dB compression point is-43 dBm. The PLL can be tuned within 1.056GHz~1.294 GHz, the phase noise is-79.69dBc/Hz@1kHz,-86.81dBc/Hz@10kHz,-99.10dBc/Hz@100kHz and-123.48dBc/Hz@1MHz. There is a 72 dBc spur at 10 MHz offset, caused by the off-chip crystal oscillator. The IF filter works at 46 MHz with a 3dB bandwidth of 34MHz~59MHz, the in-band ripple is less than 1dB, and the image rejection ratio is 32 dB. The AGC loop provides a dynamic range of 62 d B with a gain step of 2dB, and the settling time is less than 32μs. The measurement results validate the correctness and effectivity of the research work in this dissertation.