Research On DBPM System In Accelerator Beam Diagnosis

Synchrotron radiation facility is a high quality light source for the need of many scientific researches and technological innovations.Beam diagnosis system,which is used for diagnosing beam parameters and improving running status,is important to synchrotron radiation facility.And beam position diagnosis is a key part to beam diagnosis system.Its measurements cover trajetory, first turn,equilibrium,turn-by-turn,beam based alignment and orbit stability.Beam position diagnosis is performed by Beam Position Monitor(BPM),which consists of two parts:detecting sensor and signal processing system.Shanghai Synchrotron Radiation facility(SSRF) is a third-generation of synchrotron radiation light source and would be the invaluable tools for Chinese scientific research and industry community.This paper research is a subproject of "Research on advanced accelerator beam diagnoses techniques".It deals with fully digital implementation of position sensor signal processing.The goals is developing prototype of digital beam position monitor,which can be used on SSRF and SINAP.There are several generations of BPM,staring with analog signal processing.And digital signal processing took the place of analog processing gradually.In recent years,BPM development has a tendency of full digital implementation.The paper research discusses details of various techniques and implementations for digital beam position monitor.In first chapter the background of BPM was introduced,including kinds of measurement and the transform from beam position to voltage on detecting sensor.The second chapter introduced there most common processing methods for BPM processing:Δ/Σ,AM-PM and Log-ratio.TheΔ/Σis suitable for close-orbit measurement and deals with amplitude of signal.It can use the theories and techniques of communications.It is the method for BPM system of this paper.In the third chapter it was introduced that requirements of BPM system on SSRF.It is planed that two kinds of BPM will be developed.The first one is based on undersample technique which is well-developed in communications.It consists of three parts:analog signal conditioning module, ADC module and digital motherboard.The second one is a bunch by bunch BPM.It is more complicated with analog signal conditioning and A/D conversion.But the two kinds of BPM share a same kind of motherboard.So it needs well-planned when designing the motherboard.The hardware techniques used in undersampling BPM was discussed in the fourth chapter. About the analog signal conditioning module implementation mothed for narrow band pass filter of 500MHz center frequency and digitally controlled variable gain circuit were introduced.The RF circuit matching and cascading methods as well as PCB layout considerations were discussed and several S parameter simulation results were post.The ADC sampling clock was an important part of ADC module.The impact of sampling clock on ADC performance was discussed.The principle of sampling clock design for two kinds of BPM was given.The analysis of phase noise in PLL circuits was also included.Another consideration for ADC module was heat sinking design of LDOs.The motherboard was designed with improved data throughput.Some design thoughts were given about high bandwidth ADC data receiving in bunch by bunch BPM.DDRII SRAM and DDR SDRAM's interface with FPGA,including PCB layout design and logic design was discussed.How to keep the signal integrity was the main part of this section.Different kinds of simulation were done in design process,including electromagnetic simulation for PCB,IBIS simulation for HSTL signals.Ground bunch analysis was given for FPGA IO design.Digital down converter(DDC) is the key part to DSP of DBPM.The implementation of DDC in FPGA with area consideration was introduced in the fifth chapter.NCO,CIC decimator and 498 order FIR decimator was designed and implanted in FPGA.Modelsim simulation results were given.In the sixth chapter,the test report of debugged part of DBPM was given,including filter and gain control performance of analog signal conditioning module,ADC sampling clock phase noise analysis,DDRII SRAM and DDR SDRAM performance,DDC performance and whole system test.It is reckoned from the system test result that 1um turn-by-turn uncertainty could be achieved, which meets the SSRF demand.