Research On Partially Parallel Decoding Algorithm Of LDPC Code Based On Stochastic Computation

LDPC(Low Density Parity Check)code is essentially a linear block code,which has experienced more than 60 years of development.The decoding performance of LDPC approaches the Shannon limit,and LDPC has extremely low error floor.LPDC together with the Polar code replaces the Turbo code in the fourth generation mobile communication and these technologies turn into the channel coding technology in the fifth generation mobile communication.Since the birth of LDPC,its decoding algorithm has always been a focal point of research.The best decoding algorithm for LDPC codes is the SPA(Sum Product Algorithm)algorithm or BP(Belief Propagation)decoding algorithm,but its hardware implementation complexity is too high to be realized.A simplified MSA(Min Sum Algorithm)developed from BP decoding algorithm and the various improvements of MSA are the decoding algorithms applied in actual implementation.They replace the complex operations of the check nodes in the BP algorithm by finding the minimum value,however,the decoding implementation of a full-parallel MSA algorithm consumes much larger hardware area,thus the MSA-based partially parallel decoding algorithm is more commonly used.Stochastic computation maps complex operation to simple logic gates.In recent years,the application of stochastic computation to LDPC decoding is an emerging technology.Due to the natural bit-serial feature of stochastic computation,the difficulty of data routing is reduced and the pressure on hardware wiring is eased.However,the early stochastic computation LDPC decoders have a great loss in bit error performance,and can only decode some simple short codes,mainly due to the latching problem in stochastic computation decoding algorithm.MTFM(Majority-Based Tracking Forecast Memory)algorithm and stochastic computation decoders based on bitstream correlation analysis and other enhanced stochastic computation decoders optimize bit error performance by optimizing the re-random structure.However,there are many problems to be solved in decoders based on stochastic computation.First of all,so far almost all decoders based on stochastic computation are fully parallel decoding algorithms implemented on the regular codewords of(2048,1723).For irregular code patterns,the decoder based on stochastic computation is difficult to implement,because the variable nodes of each degree require the design of a specific structure.On the other hand,for very long code patterns,even the stochastic computation decoder is difficult to implement in full parallel mode,and the hierarchical decoding algorithm can hardly be applied in the stochastic computation.Given the problems mentioned above,this paper proposes a hybrid stochastic computation decoding algorithm,which combines the advantages of the MSA algorithm and the advantages of stochastic computation decoding algorithm.It applies the MSA algorithm in the variable nodes for 'Sum' operation,corresponding to the saturated adder in hardware implementation.At the check nodes,it applies the stochastic computation technique according to the correlation analysis of the bitstreams,to generate fully correlated bitstreams.Then these bitstreams are input to the AND gates and the XOR gates to operate on the bitstreams to obtain the minimum values represented by the bitstreams.The bitstreams are then converted into LLR information,which completes the 'Min' operation.Thus,the hybrid stochastic computation decoder retains the advantages of the two algorithms.Moreover,the partially parallel algorithm proposed in this paper can flexibly adjust the parallelism level of the check node process units.In traditional implementation,one row in the parity check matrix is processed each time.The first scheme of this paper,P rows of parity check matrix are processed each time,and the LUTs resources used are 2times of the traditional implementation and the Registers are 5.4 times of the traditional implementation.However,the throughput and hardware utilization efficiency is greatly improved.In order to take full advantage of the high level of parallelism which the hybrid stochastic partially parallel algorithm achieves,the number of check node units in the design of second scheme in this paper is equal to the maximum expansion factor of 5G NR LDPC.In this case,the resources of LUTs and Registers are 2 times and 4.7 times of that of the first scheme respectively,but the utilization efficiency is increased by 8 times and 5.7 times respectively.Furthermore,the hardware utilization efficiency is also higher than that of the traditional OMSA algorithm implementation.Additionally,since the proposed hybrid stochastic computation decoder is based on the MSA algorithm,it is fully compatible with the decoding algorithm of the row and column hierarchy,which can further accelerate the decoding convergence.Simulation results show that under the same decoding performance,the partial parallel scheduling can save half the number of iterations.In this paper,the maximum iterations of both columnlayered and row-layered hybrid stochastic partial parallel decoding algorithm are set to 10,and the maximum number of iterations of fully parallel hybrid stochastic decoding is set to20.All methods reach the same decoding performance.Furthermore,this paper proposes a method to resolve memory access conflicts in row-layered partially parallel decoding algorithms,which can reduce the number of clocks required per iteration.On the other hand,we can apply the inter-frame parallel technology to the hardware implementation of the algorithms proposed in this paper.The parallel processing of several frames of data from the same code type can also improve the throughput.When the expansion factor is less than or equal to 192,it can multiply the throughput.