Research On RS Decoding Algorithms And RS-LDPC Joint Decoding Algorithms Based On Stochastic Computation

Reed-Solomon(RS)codes have been widely used in communication systems due to their excellent random error and burst error correcting ability.Low-density Parity-check(LDPC)codes have been incorporated into the channel coding scheme by the 5G communication standard due to many advantages,such as low error floor and high throughput rate.In existing decoding schemes,due to complexity issues,RS codes mostly use hard-decision decoding algorithms,and LDPC codes mostly use a partially parallel decoding architecture,which is difficult to meet the high-speed and ultra-high-speed applications of future communications.The decoding algorithm based on stochastic computation can reduce the hardware implementation complexity,and improve throughput rate.Therefore,this thesis studies and improves the existing stochastic decoding algorithms for RS codes,and explores a novel stochastic RS-LDPC joint iterative decoding algorithm.The innovations of this thesis are as follows:(1)The stochastic Chase algorithm can significantly reduce the complexity of original Chase soft decoding algorithm while ensuring the decoding performance,so that the RS soft decoding algorithm can be practically applied.However,the performance of the stochastic Chase algorithm is directly proportional to the number of test vectors,while its decoding latency and computational complexity increase with the increase of number of test vectors.To address this problem,this thesis proposes the early output stochastic Chase algorithm based on Cyclic Redundancy Check(CRC)and threshold judgment,which can achieve successful decoding without generating all test vectors.The simulation results show that the algorithm proposed in this thesis can approach the frame error rate performance of the original stochastic algorithm while reducing the average iteration number to nearly 1/? of the original algorithm(? is the number of test vectors)at most.(2)When the symbol-level stochastic Chase algorithm(SSCA)of RS codes generates a test vector under high-order modulation,the search range of each symbol will increase exponentially as the modulation order and code length increase,thereby increasing the calculation complexity and storage overhead.To alleviate the computational complexity and storage pressure of the SSCA algorithm,this thesis reduces the search range by determining the search radius-assisted selection method,and proposes the 3?-SSCA algorithm.The simulation results show that for 256-QAM,the proposed algorithm reduces the search range of each symbol in a test vector from 256 to 1 at most while approaching the performance of SSCA,which reduces the storage overhead and calculation precision requirements.(3)For the application of RS-LDPC concatenated codes,further optimization of the existing decoding algorithms is required in terms of decoding complexity and performance.This thesis proposes a stochastic RS-LDPC joint iterative decoding algorithm based on stochastic computation.The algorithm inherits the advantages of low complexity of the stochastic LDPC decoder,and take advantage of the feature of RS stochastic decoding algorithm that the hard decoder can be used to approximate the soft decoding performance.The decoding performance can be improved through the joint iterative decoding architecture.This thesis designs a test vector generation method based on LDPC probability values,and a novel additional extrinsic information generation mechanism for stochastic LDPC variable nodes.The simulation results show that the proposed stochastic joint iterative decoding algorithm can obtain a gain of 0.3?0.5dB compared with the RS-LDPC concatenated decoding scheme using floating-point Belief Propagation(BP)and B erl ekamp-Mas sey(BM)hard-decision decoders.Its implementation complexity is only the sum of the complexity of a stochastic LDPC decoder and multiple RS hard decoders.Compared with the existing decoding algorithm of RS-LDPC concatenated codes,it has the advantages of low hardware implementation complexity and high hardware efficiency.