Design And Implementation Of DMA In High-speed Network Interface Card Based On CXL

Facing the problem of huge amount of data and rapidly increasing network traffic in the modern network,higher requirements are put forward for the total bandwidth and transmission delay of the data transmission link of Network Interface Card(NIC).In order to improve the data transmission performance,here we use Compute Express Link(CXL)as the data bus,and complete the design of Direct Memory Access(DMA)in the CXL-based high-speed NIC.The transmission efficiency of the system is improved by reducing the transmission link delay and cutting down the processing overhead of the Central Processing Unit(CPU).This thesis firstly carries on the theoretical analysis to the CXL bus protocol,selects the input and output sub-protocol(CXL.io)as the system transmission link,and then implements the protocol of the CXL.io transaction layer and link layer,including the assembly and disassembly of transaction layer packets and link layer packets;flow control mechanism;transaction ordering rules;link state management and flow control initialization;and the fault tolerance and retransmission(Ack/Nak)mechanism.Aiming at dealing with the problem of link congestion,weak transaction ordering is implemented in the CXL.io transaction layer to realize the scheduling of the transmission order of different types of transaction packets.At the same time,combined with the Scatter-Gather DMA technology to realize the descriptor mechanism,the fragmented small messages in the memory can be aggregated and transmitted at one time,thereby reducing the number of interactions between the NIC DMA and the CPU.Then,the design of a high-performance DMA controller is realized on basis of Scatter-Gather DMA,and the CPU is notified to update the content of the descriptor in the system memory in time to achieve the effect of reducing the message processing overhead of the CPU.Finally,the system is tested and verified on the simulation verification platform based on the bus function model(BFM)and the hardware test platform based on Field Programmable Gate Array(FPGA).The results show that the function of the system is correct,the maximum effective transmission bandwidth is 25 Gbps,the maximum data transmission delay is 30.79?s,and the transmission delay is reduced by about 40.2% compared with the traditional structure at 256 bytes transmission.