Design And Implementation Of A RISC Processor Based On MIPS64 Instruction Subset

MIPS is one of the most popular RISC processors in the world. It uses a reduced instruction set architecture to design chips. Compared with Intel who uses complex instruction set computer structure, RISC is simple in design, and has shorter design cycle. More advanced technology can be used to develop the next generation of faster processorsRISC processors have been widely used in embedded field, so designing more efficient MIPS processor has important practical values and economic significance. This dissertation takes the MIPS processor as the research object, improving the performance of the processor as the goal, and designs a 64-bit six-stage pipelined MIPS processor. This dissertation has accomplished the following work.First, it studies the compatibility of MIPS64 instruction set and MIPS32 instruction set, analyzes the sequential bottleneck of traditional five-stage pipelined MIPS processor, and puts forward the idea of a six-stage pipelined MIPS processor. It describes data conflicts and control conflicts in the six-stage pipelined MIPS processor, and gives the solutions. It accomplishes a complete six-stage pipelined MIPS processor with a subset of MIPS64 instruction set.Second, it gives the function simulation to processor by instruction sequence in Modelsim, and gives logic synthesis to processor in Quartus. Processor is implemented in Altera DE2 development board finally. It proves that the processor’s function is correct and structure is reasonable. It’s clock frequency is up to 81.7 MHZ in DE2.Third, it studies the cache structure and comes up with the idea of two level data cache and instruction cache. It also describes the working principle and state transition of the cache in detail.