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Research On High-precision And Low-resource Implementation Methods Of Channel Emulator

Posted on:2022-06-22Degree:MasterType:Thesis
Country:ChinaCandidate:W Q JiaFull Text:PDF
GTID:2518306338467524Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
With the development of 5G technology,a large number of new services and application scenarios have emerged,such as unmanned driving and telemedicine,etc.At the same time,new wireless communication equipment will be updated accordingly,while the uncertainty and complexity of wireless channels bring great difficulties to the testing of communication equipment.The channel emulator can accurately control the propagation characteristics of the channel in the laboratory scene,which can effectively solve the testing problems of the equipment and improve the efficiency of the research.However,the bandwidth of existing channel emulator is limited,and the delay accuracy is not enough.Moreover,the number of channels and paths of 5G channel models has been greatly improved compared with the previous ones,which also increases the resource consumption of the channel emulator.Therefore,this thesis mainly focuses on how to improve the delay accuracy of the channel emulator and reduce its resource consumption,the major work and contributions of this thesis includes:1.The realization of fractional delay function with high precision.In order to simulate the channel environment under the new service scenario,higher multipath delay resolution of channel model is required.However,the bandwidth of the channel emulator is limited,so it is necessary to find a solution to distinguish the tiny multipath interval under the limited bandwidth.Therefore,this thesis carries out the research on the fractional delay function with high precision at first.FIR filter,which has strict linear phase characteristics,can well achieve the fractional delay function.FIR filter has a variety of forms of implementation,different implementations have their own emphases.In this thesis,the window function method,the maximum flatness method and the Farrow architecture method are used to design the filter with fractional delay respectively.In addition,the advantages and disadvantages of different methods are compared.More importantly,the thesis presents the applicable scenarios of various methods.The above algorithms are verified in software and implemented in hardware.Considering the inefficient utilization of resources caused by the inability of multiple channels to share FIR filters,this thesis proposes a method of using multi-phase clock to realize the fractional delay function.Sampling the same signal through multiple low-frequency clocks with different phases,which is equivalent to increasing the bandwidth of the clock.The design of this method is simple,and the clock can be shared by each channel,which not only improves the accuracy,but also reduces the resource consumption of the channel emulator.In this thesis,the method is designed into modules,and the realization of each module is verified by hardware simulation.2.Resource optimization of channel emulator.The 5G model has larger antenna connections,more channels and more paths,and at the same time,the consumption of resources is also doubled.However,the pace of development of hardware devices is far behind the requirements of new business scenarios,so it is necessary to make more use of limited resources.Consider that the FIR filters cannot be shared by each channel,some scarce resources used for multiplication and addition operations,such as DSP48E1s,become the bottleneck of the large-scale development of this module.In this thesis,FIR filter is designed by using distributed algorithm,and the function design of the multiplier is completed by look up table,which avoids the use of the scarce resources mentioned above.At the same time,with the increase of the delay,the order of the filter is improved,and the use of distributed algorithm is limited.Therefore,this thesis proposes two strategies for improvement,by dividing the look up table and transforming the look up table,the distributed algorithm is optimized and the consumption of resources is further reduced.This thesis focuses on the research of channel emulator with high-precision and low-resource,and proposes effective solutions to some technical problems,which has certain reference value for the development and optimization of some functions of the channel emulator.
Keywords/Search Tags:channel emulator, fractional delay, resource optimization, distributed algorithm, FPGA
PDF Full Text Request
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