Implementation Of Wireless Channel Emulator Based On FPGA For High Delay Resolution

The channel eimulator can reproduce the propagation characteristics of wireless channels in the laboratory and has been widely used in wireless channel modeling and communication equipment testing.With the development of the fifth generation(the fifth generation,5G)mobile communication technology,Multiple Input Multiple Output(MIMO)technology has gained more attention and development.The performance of the MIMO system is closely related to the wireless channel environment.In order to simulate the environment of the wireless channel rich scatterer,the multipath delay resolution of the wireless channel model is higher and higher,which puts higher requirements on the channel emulator.Any delay of the input signal is achieved without increasing the clock frequency of the current hardware system.Based on the principle of software radio,the thesis introduces the software and hardware platform of channel emulator,takes the function of channel emulator baseband FPGA module as the starting point,analyzes the difficulties brought by the introduction of MIMO technology to the implementation of the channel emulator,the three modules of channel emulator multipath delay,baseband FPGA and DSP data communication function implementation and channel emulator baseband function module joint debugging are combined to design and implement related modules.The main research work of the thesis has the following thr-ee aspects:1.Implementation of the channel emulator multipath delay module.The range of the multipath delay in the wireless channel model is relatively large.In the channel emulator,the multipath delay can be divided into integer delay and fr-actional delay according to the hardware system clock frequency.The integer delay is based on three storage structures:FIFO,dual-port RAM,and SDRAM.It is implemented by first writing and then reading out under clock drive.Under the premise of not modifying the hardware clock frequency,by analyzing the performance of two kinds of FIR filters based on windowed sinc function method and Farrow architecture method,the fractional delay simulation with accuracy of Ins is realized on the hardware and the error analysis is completed.2.Implementation of channel emulator baseband FPGA and DSP data communication function.In the channel emulator,the baseband processor is composed of two parts,FPGA and DSP,which fully exploits the advantages of DSP processing complex data,high concurrency and high real-time performance of FPGA.The DSP completes the calculation of the channel tap coefficient increment and the conversion of the floating point number to the fixed point number.The FPGA performs tap coefficient interpolation to achieve frequency matching with the input signal,multipath delay,and wireless channel convolution.Based on the RapidIO heterogeneous transmission protocol,the thesis transmits the fixed-point number processed by the DSP to the FPGA according to the specific frame format,and tests the electrical characteristics of the hardware interface and the user logic function to realize the data communication function between the baseband FPGA and the DSP.3.Channel emulator baseband module system joint debugging.After implementing the above two functions and combining with the existing foundation of the laboratory,the thesis completes the joint debugging of the baseband function module of the wireless channel emulator and tests and analyzes the overall function of the channel emulator baseband module.