The Research On The Low Power Physical Design Of VLSI Chip On Nanoscale Processes

With the continuous development of integrated circuit technology, the transistor feature size is shrinking and the number of transistors per unit area on chip is bigger. When the transistor feature size decreased to the nanometer level, the number of transistors on some VLSI chip is hundreds of billions. At the same time, the static power consumption caused by leakage current has risen sharply due to the characteristics of the transistor size shrinking, which makes the power at this stage in the design of IC attracting more attention. The power consumption will affect chip package and cost, and the increasing power result in a series of problems, such as EM issue which reducing the reliability of the chip.These factors make IC designers have to do more work on the study of the power consumption in chip design.Firstly, this paper introduces the challenges faced by low power technology, the research status at home and abroad and the significance of the low power research. Secondly, analyzes the power consumption, and discusses the method of reducing power consumption from the semiconductor technology level, circuit level and gate level and system level. Then this paper briefly introduces the low power physical design flow based on Golden UPF (Unified Power Format). And we complete sblk_dfttr_vdci module from Netlist to GDS2 by using this flow.And then this paper introduces how to implement the multi-voltage and power switch technology, especially the process of creating voltage area, inserting level shifter and inserting isolation cell ctc. Finally, analyzes the total power consumption and the power integrity.For the verification of the total power consumption, we use Synopsys’s PrimetimePX tool, the results of the analysis show that can completely satisfy the power requirement of the module; For the integrity of the power consumption analysis, we mainly analayzes this from two aspects:voltage drop and electron mobility.From the analysis results of Apache Redhawk tools, both the dynamic and static voltage drop and electron mobility meet the requirements of the design.The highlight of this paper lies in:for the sblk_dfttr_vdci module of TSMC 28 nm process, we adopt a new low power physical design flow based on Golden UPF, and completed Multi-voltage and power switch low power technology in the module design. In this article, we describe the multi-voltage technology and power gating in the physical implementation of the emergence of some important and difficult issue of depth. Especially for creating voltage domain, inserting level shifter, level shifter input and output power connection, the power switch cell insertion and isolation cell insertion, this paper provides detailed implementation process. This can provide some reference for the physical design engineer who need this and lay the foundation for future projects.