The Research And Implementation Of Low Power Methodology Based On UPF

With the continuous development of integrated circuit design technology and the progress of semiconductor technology,the integration and complexity of the chip are improved and the operating frequency is also greatly improved,which leads to the power density of the chip is significantly increased,and the power consumption of the chip is increased rapidly.Increased power consumption increases the difficulty of chip test,and puts forward more stringent requirements for the chip's heat dissipation and packaging.In addition,in order to meet the requirements of energy conservation standards and forced by the market pressure,reducing the power consumption of the chip is the trend.Power consumption has become an important factor must to be considered in VLSI design and optimization after area and speed.This topic is based on the project during the internship and studies the low-power design method of the integrated circuit and completes the low-power design of an interface module in the graphics chip.This paper first studies the composition of power consumption in integrated circuits(including static power and dynamic power)and various low-power design methods.Secondly,this paper also studies the UPF(Unified Power Format)standard and the low power design process based on UPF.By describing the power-related information in a UPF file and using the power intention provided by the UPF file in the entire integrated circuit design process,the complexity and risk of low-power design is largely reduced.And then use the following low-power design technologies for low-power design of the interface module:1)Multi-VT technology: Use Multi-VT library for synthesis,that is,use one-pass process.2)Clock Gating technology: In the logic synthesis phase,use the tool Design Compiler to insert clock gating unit automatically without modifying the RTL code.3)Multi Voltage and Power Gating technology: On the basis of the correct description of the logic function,UPF is used to describe the intent,index and parameters of low power design,and complete the logic synthesis based on UPF.Finally,complete the logic equivalence check by formal verification tool Formality between the original RTL+UPF files and the gate level netlist + new UPF file UPF' which both of them generate after synthesis,and use the tool VCS to do power aware simulation with the RTL and UPF to verify the correctness of the low-power design.In addition,based on the correct low power design,this paper draws the following conclusions through analyzing and comparing the power consumption of the low power design with different technologies with the power consumption of the module before using any low-power design method: After using the multi-threshold voltage technology,the static power consumption has been significantly improved.Clock gating technology can significantly reduce dynamic power consumption.And power gating and multi-voltage domain technology can simultaneously reduce both of the dynamic power and static power consumption,can reduce the power consumption in the maximum extent.When using power gating technology,it is not sure that the logic of the output signals of the module should be clamped to "0" or "1" by the isolation cells when the module's power is turned off.In order to solve the above problem,this paper proposes a method to generate a high reliability UPF by using static verification method to determine the clamp value of the output signals of the power-down module in a shorter time,and it has some reference value for the low-power design practice of integrated circuits.The design has achieved the desired objectives and requirements,but there are many more in-depth technologies worth studying.