Design Optimization And Verification Of Floating Point Units Based On BOOM

The birth of the RISC-V instruction set architecture brings hope to the development of the domestic CPU industry.The floating-point execution unit is a key unit in processor design.Its complex design and long execution time often affect the processor's timing performance due to excessively long critical paths.Therefore,how to improve the performance of floating-point units has become a key research direction in processor design.Based on the RISC-V architecture and BOOM instruction set,this thesis designs a floating-point execution unit that supports single and double precision and performs timing optimization and verification.The design of the floating-point unit mainly includes the design of the data path and operation module.There are 65 floating-point instructions,including floating-point multiplyadd,floating-point division and square,floating-point conversion,floating-point comparison,and floating-point storage instructions.Among them,the floating-point division designed in this thesis is improved on the radix-2 manual algorithm and is implemented using the radix 4 algorithm.Because the radix 4 algorithm can generate two quotient digits per cycle,compared with the manual algorithm of radix 2,the operation cycle is shortened by half.The floating-point fusion multiply-add component adds a leading zero prediction component on the original basis,so that the prediction of leading zero can be performed simultaneously with the addition and subtraction of the mantissa,thereby improving the efficiency of subsequent normalized shifts and reducing the operation delay.At the same time,doubleprecision multiply-add components are used to complete single-precision multiply-add operations.The implementation method is to convert single-precision numbers into doubleprecision forms before operation,and then convert to single-precision forms after operation,which causes a small increase in operation delay,But greatly reduced the area occupied.Finally,the correctness of the FPU module is verified based on the UVM verification methodology.At the same time,System-level verification is performed on the FPGA.The verification platform uses both directional and random vectors for testing.The reference uses Berkeley's Soft Float.After multiple verifications,the functional coverage reached 100% and the code coverage was 99.6%.FPGA verification also successfully passed all SPEC2006 test sets,and IPC increased by 9%.Design Compile is used for synthesis under 28 nm process. improve timing by 2.7 times,reduce area by 8.7%,reduce power consumption by 7%.