QEMU-based Functional Model For Reconfigurable Application Specific Processor

With the development of System On Chip(SoC),software emulators are now playing a more and more important role in the fields of architecture design,software/hardware co-design and verification.In the development process of Reconfigurable Application Specific Process(RASP)core,a Matlab-based computation model and a SystemC-based cycle-accurate model have been design to assist algorithm design and architecture design.However,these two models are not fit in full-system emulation with a operating system on them.In this paper,a functional model of RASP is designed and implemented based on QEMU,a quick emulator using the virtual device model named QOM(QEMU Object Model)to emulate physical devices.The functional model of RASP is divided into three levels,which are interface level,control level and algorithm level,according to the features and architecture of RASP.The interface level is designed to emulate the registers and SRAM in RASP,the control level is responsible for the main controller of RASP,and the algorithm level is responsible for the DMA module,the reconfiguration controller module and reconfigurable computing array module.In the interface level,the register functional module and internal storage functional module are designed;In the control level,a task queue is designed to assist the dispatch of the algorithms' calculation and the implementation of master mode,slave mode and debug mode;In the algorithm level,a generic working process of calculating by step is designed,and cross correlation and complex FIR algorithm units are provided as examples to show the method of implementing the algorithm units based on the functions emulating the calculation IP cores in RASP.At last,the functional model of RASP is verified both in function and performance using a convenient test case template which is implemented based on QEMU's Qtests.In this paper,a high performance functional QEMU-based model of RASP is designed and implemented,which has the same function and calculation accuracy as the SystemC-based cycle-accurate model without the details of working and gets a performance improvement about 3?6 times against the SystemC-based model in the execution of the algorithm instructions with little data amount,about 10?30 times in those with large data amount.