Verification Of Algorithms In The Reconfigurable Application Specific Processor Based On UVM

With the increasing complexity of integrated circuit,the verification of chip is becoming heavier and heavier.Even more worrying is that the gap between design capability and verification capability is becoming greater.Verification has become the key point which restricts the development of integrated circuit.At present,verification has occupied 60%-80%in the period of designing a chip.Because of this,the industry put forward the concept of verification platform which can raise the efficiency of verification by automatizing verification.After more than ten years of development,a perfect methodology of verification has formed and we call it UVM.At first,this article introduces a reconfigurable application specific processor which the FIR algorithm verifying in the article is realizing on.Then the article introduces the basic theory of verification and points out the difference between verification and test.Also,the article explains the concept of functional verification in detail and clarifies three important stages in the development of verification.The article emphasizes the importance of coverage in verification and introduces the history of the verification language and the verification platform.After this the article introduces the architecture of UVM and describes the relationship among components in UVM using tree diagram.At the same time,the article also introduces various mechanisms in UVM.Then,the article introduces the principle of two FIR algorithms and explains their implementation on RASP.Moreover,the article abstracts some groups of points and order which can be treated as the guide of verification according to the implementation.Finally,the article introduces the architecture of the verification platform in macro view and the usage of components in platform.Meanwhile,the article clarifies the execution flow by using some piece of code and for example,the article selects the group(16,16)to explain the whole process of verification in detail and gives the result and coverage information to prove the correctness of the design.