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Research On Secure Processor Architecture And VLSI Implementation Of Low Power Dedicated Instruction Set

Posted on:2010-08-08Degree:MasterType:Thesis
Country:ChinaCandidate:L HanFull Text:PDF
GTID:2208360275492234Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the rapid popularization of information security technologies, cryptographic algorithms have been used in more and more domains. Some hardware solutions, such as application specific integrated circuits (ASICs), can easily achieve the functionality and performance requirement, but they lack the flexibility, configurability and extensibility over the lifetime of these devices. General purpose processors, on the other hand, provide a flexible solution, but they take much more area and consume more power than dedicated hardware solutions. A reasonable solution should be selected under a range of concerns, including performance, cost, power consumption and extensibility. A promising approach is to use security domain specific processors which are dedicatedly designed based on programmable processors.A low-cost, low-power, high-performance security processor based on application specific instruction set processor architecture is proposed in this paper, which is suitable for several kinds of embedded security systems. First of all, this paper analyzes public-key, symmetric-key and hash cryptographies, distills and optimizes the critical steps of typical algorithms. Secondly, as to the processor’s architecture, this paper optimizes the data path of processor, proposes unified RSA/SHA crypto function unit, special ALU and parallel lookup tables to accelerate the execution of these critical steps in minimal hardware cost. Thirdly, the dedicated cryptographic instructions contained in the specific instruction set architecture of this processor can significantly improve the performance of cryptography algorithms and achieve high flexibility of software. Finally, such techniques as freezing unused function unit and bypassing dummy operation are utilized at system and architecture level to decrease power consumption.The proposed design achieves the goal of high-performance, high-flexibility, low-power and low-cost. Therefore, it has a good prospective for application in security embedded systems.
Keywords/Search Tags:Information Security, RSA, AES, SHA-1, Embedded Processor
PDF Full Text Request
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