Study And Design Of RISC-V Based Convolutional Neural Network Application Specific Instruction-Set Processor

Compared with x86 and ARM architecture,RISC-V can be customized and optimized for different application domains at lower cost.In recent years,RISC-V has become a research hotspot for domestic and foreign research institutions and enterprises.On the other hand,artificial intelligence,as the most popular science and technology today,has already penetrated into various industries and produced many intelligent products.However,in the current mainstream computing platforms,GPU power consumption and cost are too high,FPGA resources and speed are limited,and ASIC has poor generality.The CPU platform with deep technology accumulation is more suitable for domains that are cost-sensitive and have flexible algorithms or complex calculation.However,the current general-purpose CPUs are difficult to meet the large-scale calculation of neural networks.To solve above problems,this thesis proposed Domain Specific Architecture(DSA)which is an application-specific instruction set processor based on the open source instruction set RISC-V for low power applications of Internet of Things and artificial intelligence applications of convolutional neural network.This processor can accelerate CNN algorithm and improve power efficiency of terminal.The main study contents are as follows:(1)Study the mainstream instruction set architecture processors,analyze the methods to enhance the CPU performance,improve the parallelism,and the existing convolutional neural network acceleration schemes.In addition,the operation process and lightweight method of convolutional neural network is studied and analyzed,and the application-specific expansion instruction and RISC-V open source processor customization schemes are designed.(2)Aiming at the characteristics and basic operations of lightweight models,the architecture and control methods of the convolutional neural network accelerator are improved.The accelerator focuses on optimizing the convolution and pooling operations.Also,the information of each layer of the convolutional neural network is configured through the custom expansion instructions,and the accelerator is controlled to perform grouping operations on the input data to accommodate the input data of different sizes.Moreover,the data path of the accelerator is adjusted,and the convolution,pooling and activation operations of the convolutional neural network are operated separately or in combination to adapt to a variety of lightweight convolutional neural networks.(3)On the Genesys 2 FPGA development board of Xilinx Kintex-7 series,the RISC-V based convolutional neural network application-specific instruction set processor was verified and tested.The experimental results show that the domain specific architecture processor designed in this thesis has a power consumption of 1.966 W at 100 MHz clock and takes about 40.89 ms to infer the Squeeze Net network,which is faster than the single-core computing speed of mobile phone processors.It also consumes less resources and power on other platforms,and has an advantage in performance per watt.