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Designed And Verified Image Data Acquisition Device Based On Camera Link Protocol

Posted on:2021-05-22Degree:MasterType:Thesis
Country:ChinaCandidate:J X ZhangFull Text:PDF
GTID:2428330602465498Subject:Instrument Science and Technology
Abstract/Summary:PDF Full Text Request
This article designs a coded image data acquisition device based on the Camera Link transmission protocol: in hardware,FPGA is used as the main controller,and serial-parallel chips are used to receive Camera Link protocol image data,and DDR2 is used to complete the cache of high-speed image data.LVDS transfers the data to memory and sends it to the host computer to complete the reception of image data.This paper first analyzes the functional requirements of the acquisition device,and proposes an image data acquisition device based on the Camera Link interface.This article mainly receives three serial differential data receptions from the Camera Link protocol,image data buffering,and high-speed data long-distance transmission.Discussion and research.Firstly,it analyzes the transmission characteristics and principles of the Camera Link interface,selects the serial-to-parallel conversion chip and completes its peripheral hardware circuit design;secondly,it introduces the application of the data cache technology in this design,and chooses to use the DDR2 cache technology by comparison.In the design,the write logic and read logic of DDR2 are introduced in detail on the basis of analysis of the data stream;in the transmission of image data,two data transmission methods of real-time data forwarding to the host computer and storage to the storage device are designed,in which By using the characteristics of LVDS long-distance transmission,the received data is sent to the host computer in a serial manner and transferred to the storage device for read back.In order to facilitate data analysis,data framing is completed before data transmission.Finally,a verification platform was built,and a simulated image data source was designed to perform performance tests on the device.The simulated image data source sent fixed format data at a 55 MHz clock,and the read-back data was analyzed by the host computer software to verify that the device can achieve high-speed image data editing and editing,which meets The design requirements are characterized by accurate data reception,strong real-time performance and high reliability.
Keywords/Search Tags:Camera Link, FPGA, DDR2, LVDS data transmission
PDF Full Text Request
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