The Design And Implementation Of LDPC Of LDPC Encoder And Decoder

“Low-Density Parity Check(LDPC)”coding technology is one of the most important achievements in the field of channel coding and information theory.It has similar or even better decoding performance than Turbo coding scheme.Comparing Turbo code,the decoding delay of LDPC is shorter than Turbo and its advantage also resides in favorable code distance,lower decoding complexity and flexible adjusting method in code rate and code length aspect.Based on these benefits,LDPC has been adopted in many telecommunication standards like 5G-NR,802.11 an,802.11 ad etc.To meet the demand of increasing data-transmission speed,the LDPC encoding and decoding algorithm should be both implementable and effective,which means guaranteeing the same decoding performance and data throughput after being implemented.In this article,it discusses and researches on the encoder and decoder implementation based on the QC-LDPC in the 802.11 ad standard.For the encoder,it utilizes the “part-inverse matrix”to re-arranged the data calculating and processing procedure under the condition of keeping the Quasi-Cyclic and sparse property of the matrix.Comparing with the classical encoding scheme directly using the parity-check matrix,the propsaled method achieves better performances when considering the hardware resource utilization.The critical part of LDPC hardware implementation is the decoder design.There are two mainstream architectures for LDPC decoder design so far: traditional min-sum algorithm and newly discovered stochastic computation algorithm.The big hardware area and congestive routing wire bottleneck exist in the min-sum architecture,which limit the datathroughput of the decoder,the stochastic computation method can mitigate the problem via denoting the data in the form of the single stochastic bit stream during the decoding.However,long decoding delay and the“latch-state”problem at the input of variable node process unit makes the fully stochastic computation architecture converge slow.In this thesis,it designs and implements one Relaxed-Half Stochastic(RHS)architecture.RHS absorbs the merits of both min-sum and fully stochastic computing methods,which make the algorithm gain better performance in the aspects of hardware area and data-throughput.In RHS algorithm,the train of the thought of the variable node design also bases on the LLR-BP algorithm,which is same to min-sum way but uses the stochastic computation and stochastic single bit to represent data to layout the check node unit structure,of which complexity is high in min-sum method.According to this factor,the width of the connected wire network is in the form of single bit that leads the decoder to good timing convergence.it also optimizes the RHS for the LDPC in 802.11 ad,simulates and verifies some key parameters for the algorithm,compares the decoding performance of two different initiation strategies.The fixed-point simulation is also researched,which proves that the RHS is valid for the short-length LDPC.In the last,it takes some optimizing measures based on FPGA platform to implements the RHS decoder on the Xilinx FPGA chip.In addition to above,the effectiveness of “one-step”initialization strategy for the fully stochastic architecture based on the counter is verified and the corresponding decoder is also designed and implemented on the Xilinx FPGA chip.