Design And Implementation Of Encoder And Decoder For QC-LDPC With High Efficiency And Low Complexity

With the rapid development of mobile communication technologies,while bringing more convenience to people,the ever-increasing demand for data and business demands have made mobile communication technology necessary for the development of The Next-generation Mobile Communication Technologies(5G).Channel coding technology can improve the performance of the communication system and improve the quality of the communication system.Selecting an appropriate channel coding solution has become an important link.Rely to its excellent error correction performance,the Low-Density Parity-Check(LDPC)code has become a long code block coding scheme for Enhance Mobile Broadband(eMBB)service data information in 5G.In this paper,encoding and decoding algorithms are combined with hardware simulation,and quasi-cyclic LDPC(QC-LDPC)codes under the IEEE 802.16 e standard are used for encoding and decoding.The traditional QC-LDPC encoder has the problems of high coding algorithm complexity,low throughput,and high hardware resource consumption.To solve those problems,a high-throughput low-complexity QC-LDPC encoder is proposed.In the design,a parallel processing hardware calculation structure between rows and columns is used to calculate the intermediate variables.This improved encoder structure can effectively reduce the encoder's occupation of logic resources and memory resources while improving the parallelism of encoder.The design also optimizes the calculation of the check digits,so that the throughput of the encoder has been further improved.In terms of decoder,in order to balance the complexity of hardware implementation and the throughput of decoder,thought the hardware structure design adopts a partial parallel structure,the decoding algorithm uses the Normalized Minimum Algorithm(NMSA).In the hardware implementation(FPGA or ASIC)of the NMSA,proper blocking can increase the degree of parallelism and improve the throughput of decoder.The simulation results show that for IEEE 802.16 e QC-LDPC codes with a code length of 2304,on a Xilinx XC7VX485 T chip,the design can achieve an encoder with a clock frequency of 233.18 MHz and an information throughput of 22.36 Gbps,and the occupancy is not high.Over 5631 slice of chip logic resources and 3456 bit of RAM storage resources.The clock frequency of the decoder is 415.62 MHz,and the throughput can reach 787.26 Mbps with 10 iterations.