Investigation On Hot-Carrier Degradation Mechanisms And Lifetime Model For STI-Based LDMOS Devices

Shallow trench isolation (STI) process becomes a mainstream in deep-submicrometer power integrated circuits due to its absence of birds' beak, higher integration and better performance of isolation, making STI-LDMOS transistor be the most widely used power devices in minimum scale. However, the reduction of characteristic dimensions without reduction of operating bias makes STI-LDMOS transistor particularly susceptible to hot carrier stress (HCS) degradation. The conclusion of HCS degradation mechanism for traditional LDMOS is no longer suited to STI-LDMOS. Thereby, an in-depth research is urgently needed about the new degradation mechanism and related lifetime model of STI-LDMOS transistor.Firstly, the HCS degradation mechanism of the device is investigated basing on I/V test system and Sentaurus TCAD simulation platform. It reveals that when the device is stressed under medium Vgs, inerface trap generation (Nit) at the STI corner close to the source dominates the degradation of the device. While Nit at STI corner close to the drain is responsible for the degradation when the device is stressed under high Vgs. Also, the temperature dependence of linear drain current (Idlin) shift by hot carrier effect is investigated. Based on the results, high temperature tends to deteriorate the degradation because of the decrease of threshold voltage and then the increase of current density of the device. In addition, the appropriate method to evaluate the lifetime of the device is discussed. The worst stress condition for lifetime evaluation and more accurate monitoring method for Idlin are supposed. Accordingly, a lifetime model of STI-LDMOS is set up. The related parameters of the model are extraced and the magin of error turns out to be in 10%.Finally, some optimizations have been performed to improve the hot-carrier reliability of the device.It is found that longer length of channel or poly, more moderate slope of STI or smaller curvature of STI corners are beneficial to high reliability against HCS. Moreover, several new structures with high reliability against HCS are proposed, such as trench-gate structure, P-top layer structure and detached gate stucture.The achievements in this thesis are helpful to the investigation of hot carrier effect and design of high reliability transistor for deep-submicrometer power device.