Shallow Trench Isolation (sti) Etching Process Conditions Optimization

STI (Shallow trench isolation) technology is a new MOS integrated circuit isolation method, comparing to LOCOS(local oxide of silicon) technology.The STI technology can eliminate the bird’s beak impact in a whole flat surface condition, the insulating layer can be deeper, can reduce leakage current between the electrodes and bear a greater breakdown voltage. Now STI has become the standard device isolation technology for the production of critical dimension less than 0.25um process.The first step of shallow trench isolation process is anisotropic dry etching process to form a narrow trench in the isolating area, then using CVD technology to deposit oxide and fill the trench, followed by using the CMP process to remove excess oxide layer on the wafer surface.In this study, given the original process conditions of 0.18um technology, we have all the geometric dimensions shrink by 90%, so we will get a 0.16-micron process. As the whole film structures keep the same but CD of STI will be changed, production stability and versatility will be challenged. We need to optimize the process recipe to reach our required criteria.The experimental results shows that the STI profile can be controlled very well by means of adjusting O2 flow, and we need to adjust the Si etch processing time to meet the trench depth goal. With the optimized recipe we got the proper STI profile as required and good uniformity within wafer. After the experimental lots have passed the End of line yield and breakdown voltage test the new recipe was released to high volume production.