| The shallow trench isolation process is currently used in integrated circuit fabrication to isolate CMOS transistors. As devices become smaller, the control over process parameters become tighter. STIE characteristics of concern in this research included LER, CD etch bias, CD uniformity, and defect number. The main issue was the control of LER on 193nm photoresist. A design of experiment was created to characterize LER for this research. Three parameters in shallow trench isolation nitride etch were considered. Gas flow rates CF4, CHF3, and O2, were varied while holding other conditions constant according to the full factorial DOE. The STINITE condition that gave the lowest LER and -20nm CD bias while maintaining low CD uniformity and defect number was the 28:16:8sccm CF 4:CHF3:O2 condition. It was found that increasing O2 gas flow rate decreased LER. The tradeoff in obtaining the lowest LER was an increase in defects. |
