Reliability Research Of Cache Coherency Protocol

In multi-level caches system of cloud servers, the chip multiprocessors are vulnerable to transient faults caused by self-faults or on-purpose attacks. Based on this background, enhancing data reliability is becoming one of the hot issues in multi-level caches systems. In particular, in dual-controller storage system, how to keep data consistency in cache synchronization process is becoming one of the most important technical difficulties.In this paper, we design an additional cache system to keep redundancy data for modified and shared L2 cache lines to improve the reliability of storage systems. Based on Multi2Sim simulator, the empriments results prove that this cache can provide data reliability. Also, this cache can provide the average latency of memory hierarchy for error correction with limitted energy cost and silicon overhead. Besides, we design an improved cache coherency protocol to solve the data coherency problem in dual-controller systems. Experiments show that using the present method, data lost can be eliminated.Although the feasibility of MSR cache has already been proved in this study, the efficiency of it is still unsatisfactory. How to improve the efficiency of MSR cache needs to be studied in the future.