Tolerance Cache Research Based On Mixed ECC

Voltage scaling is one of the most effective mechanisms to improve Embedded processors’energy efficiency. However, processors cannot operate reliably as supply voltage continuously decreases, since large memory arrays(e.g., caches) may fail due to manufacturing-induced parameter variations increasing in severity. Such variations restrict voltage scaling to a minimum value, Vccmin. So reaserach for cache reliability under low supply voltage is of greate importance to the design of embedded processors. Based on this, this paper focus on the realiablity of caches under low supply voltage. The main content and innovations of the thesis include:1. Research on failure model and error injection technicals. Based on the analysis of the causes of persistent failures and non-persistent failures, this paper proposes the faiure model for experiment. It also proposes an error injection technical and realizes CK-CPU simulation by combining the research on all kinds of error injection technicals and the reality of this paper.2. Tolerance cache research based on mixed ECC. Based on the characteristic that clean lines are recoverable while dirty lines are not, this paper propose a mixed ECC based tolerance cache. This design divided Cache into two regions, one was protected by multi-bit ECC and the other was protected by single-bit ECC. It ensured that vulnerable dirty lines were always in the region protected by multi-bit error-correcting codes through a new cache replacement policy and the special disposal of write hit SECC region. Experiment results from EEMBC showed that compared to prior work VS-ECC-FIXED, this design could also work reliably at a minimum voltage of590mv. Furthermore, it also showed that this design reduced23.6%of the error-correcting storage and the performance of processor improved by5.9%averagely.